Lines Matching refs:op1
4344 vixl32::Register op1 = RegisterFrom(op1_loc); in GenerateMinMaxInt() local
4348 __ Cmp(op1, op2); in GenerateMinMaxInt()
4356 __ mov(is_min ? lt : gt, out, op1); in GenerateMinMaxInt()
4412 vixl32::SRegister op1 = SRegisterFrom(op1_loc); in GenerateMinMaxFloat() local
4422 DCHECK(op1.Is(out)); in GenerateMinMaxFloat()
4424 __ Vcmp(op1, op2); in GenerateMinMaxFloat()
4441 __ Vmov(temp1, op1); in GenerateMinMaxFloat()
4473 vixl32::DRegister op1 = DRegisterFrom(op1_loc); in GenerateMinMaxDouble() local
4479 DCHECK(op1.Is(out)); in GenerateMinMaxDouble()
4481 __ Vcmp(op1, op2); in GenerateMinMaxDouble()
4499 __ Vand(F64, out, op1, op2); in GenerateMinMaxDouble()
4505 __ Vorr(F64, out, op1, op2); // assemble op1/-0.0/NaN. in GenerateMinMaxDouble()