Lines Matching refs:in_low
3869 Register in_low = locations->InAt(0).AsRegisterPairLow<Register>(); in DivRemOneOrMinusOne() local
3876 __ Subu(out_low, ZERO, in_low); in DivRemOneOrMinusOne()
3881 __ Move(out_low, in_low); in DivRemOneOrMinusOne()
3946 Register in_low = locations->InAt(0).AsRegisterPairLow<Register>(); in DivRemByPowerOfTwo() local
3959 __ Addu(AT, AT, in_low); in DivRemByPowerOfTwo()
3960 __ Sltu(TMP, AT, in_low); in DivRemByPowerOfTwo()
3979 __ Addu(AT, AT, in_low); in DivRemByPowerOfTwo()
3980 __ Sltu(AT, AT, in_low); in DivRemByPowerOfTwo()
3993 __ Addu(AT, AT, in_low); in DivRemByPowerOfTwo()
3994 __ Sltu(AT, AT, in_low); in DivRemByPowerOfTwo()
4010 __ Or(AT, AT, in_low); in DivRemByPowerOfTwo()
4016 __ Andi(AT, in_low, 1); in DivRemByPowerOfTwo()
4017 __ Sll(TMP, in_low, 31); in DivRemByPowerOfTwo()
4024 __ Andi(out_low, in_low, abs_imm - 1); in DivRemByPowerOfTwo()
4026 __ Ext(out_low, in_low, 0, ctz_imm); in DivRemByPowerOfTwo()
4028 __ Sll(out_low, in_low, 32 - ctz_imm); in DivRemByPowerOfTwo()
4045 __ Move(out_low, in_low); in DivRemByPowerOfTwo()
4054 __ Move(TMP, in_low); in DivRemByPowerOfTwo()
4083 __ Or(AT, AT, in_low); in DivRemByPowerOfTwo()
4086 __ Move(out_low, in_low); in DivRemByPowerOfTwo()