Lines Matching refs:reg
26 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_FALSE(reg.Overlaps(reg)); in TEST()
32 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); in TEST() local
33 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
35 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
36 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
37 EXPECT_EQ(ZERO, reg.AsGpuRegister()); in TEST()
39 reg = Mips64ManagedRegister::FromGpuRegister(AT); in TEST()
40 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
41 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
42 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
43 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
44 EXPECT_EQ(AT, reg.AsGpuRegister()); in TEST()
46 reg = Mips64ManagedRegister::FromGpuRegister(V0); in TEST()
47 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
48 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
49 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
50 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
51 EXPECT_EQ(V0, reg.AsGpuRegister()); in TEST()
53 reg = Mips64ManagedRegister::FromGpuRegister(A0); in TEST()
54 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
55 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
56 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
57 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
58 EXPECT_EQ(A0, reg.AsGpuRegister()); in TEST()
60 reg = Mips64ManagedRegister::FromGpuRegister(A7); in TEST()
61 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
62 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
63 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
64 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
65 EXPECT_EQ(A7, reg.AsGpuRegister()); in TEST()
67 reg = Mips64ManagedRegister::FromGpuRegister(T0); in TEST()
68 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
69 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
70 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
71 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
72 EXPECT_EQ(T0, reg.AsGpuRegister()); in TEST()
74 reg = Mips64ManagedRegister::FromGpuRegister(T3); in TEST()
75 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
76 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
77 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
78 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
79 EXPECT_EQ(T3, reg.AsGpuRegister()); in TEST()
81 reg = Mips64ManagedRegister::FromGpuRegister(S0); in TEST()
82 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
83 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
84 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
85 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
86 EXPECT_EQ(S0, reg.AsGpuRegister()); in TEST()
88 reg = Mips64ManagedRegister::FromGpuRegister(GP); in TEST()
89 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
90 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
91 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
92 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
93 EXPECT_EQ(GP, reg.AsGpuRegister()); in TEST()
95 reg = Mips64ManagedRegister::FromGpuRegister(SP); in TEST()
96 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
97 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
98 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
99 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
100 EXPECT_EQ(SP, reg.AsGpuRegister()); in TEST()
102 reg = Mips64ManagedRegister::FromGpuRegister(RA); in TEST()
103 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
104 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
105 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
106 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
107 EXPECT_EQ(RA, reg.AsGpuRegister()); in TEST()
111 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST() local
113 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
114 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
115 EXPECT_TRUE(reg.IsFpuRegister()); in TEST()
116 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
117 EXPECT_TRUE(reg.Overlaps(vreg)); in TEST()
118 EXPECT_EQ(F0, reg.AsFpuRegister()); in TEST()
119 EXPECT_EQ(W0, reg.AsOverlappingVectorRegister()); in TEST()
120 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
122 reg = Mips64ManagedRegister::FromFpuRegister(F1); in TEST()
124 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
125 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
126 EXPECT_TRUE(reg.IsFpuRegister()); in TEST()
127 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
128 EXPECT_TRUE(reg.Overlaps(vreg)); in TEST()
129 EXPECT_EQ(F1, reg.AsFpuRegister()); in TEST()
130 EXPECT_EQ(W1, reg.AsOverlappingVectorRegister()); in TEST()
131 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F1))); in TEST()
133 reg = Mips64ManagedRegister::FromFpuRegister(F20); in TEST()
135 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
136 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
137 EXPECT_TRUE(reg.IsFpuRegister()); in TEST()
138 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
139 EXPECT_TRUE(reg.Overlaps(vreg)); in TEST()
140 EXPECT_EQ(F20, reg.AsFpuRegister()); in TEST()
141 EXPECT_EQ(W20, reg.AsOverlappingVectorRegister()); in TEST()
142 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F20))); in TEST()
144 reg = Mips64ManagedRegister::FromFpuRegister(F31); in TEST()
146 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
147 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
148 EXPECT_TRUE(reg.IsFpuRegister()); in TEST()
149 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
150 EXPECT_TRUE(reg.Overlaps(vreg)); in TEST()
151 EXPECT_EQ(F31, reg.AsFpuRegister()); in TEST()
152 EXPECT_EQ(W31, reg.AsOverlappingVectorRegister()); in TEST()
153 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
157 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); in TEST() local
159 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
160 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
161 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
162 EXPECT_TRUE(reg.IsVectorRegister()); in TEST()
163 EXPECT_TRUE(reg.Overlaps(freg)); in TEST()
164 EXPECT_EQ(W0, reg.AsVectorRegister()); in TEST()
165 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister()); in TEST()
166 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
168 reg = Mips64ManagedRegister::FromVectorRegister(W2); in TEST()
170 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
171 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
172 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
173 EXPECT_TRUE(reg.IsVectorRegister()); in TEST()
174 EXPECT_TRUE(reg.Overlaps(freg)); in TEST()
175 EXPECT_EQ(W2, reg.AsVectorRegister()); in TEST()
176 EXPECT_EQ(F2, reg.AsOverlappingFpuRegister()); in TEST()
177 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W2))); in TEST()
179 reg = Mips64ManagedRegister::FromVectorRegister(W13); in TEST()
181 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
182 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
183 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
184 EXPECT_TRUE(reg.IsVectorRegister()); in TEST()
185 EXPECT_TRUE(reg.Overlaps(freg)); in TEST()
186 EXPECT_EQ(W13, reg.AsVectorRegister()); in TEST()
187 EXPECT_EQ(F13, reg.AsOverlappingFpuRegister()); in TEST()
188 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W13))); in TEST()
190 reg = Mips64ManagedRegister::FromVectorRegister(W29); in TEST()
192 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
193 EXPECT_FALSE(reg.IsGpuRegister()); in TEST()
194 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
195 EXPECT_TRUE(reg.IsVectorRegister()); in TEST()
196 EXPECT_TRUE(reg.Overlaps(freg)); in TEST()
197 EXPECT_EQ(W29, reg.AsVectorRegister()); in TEST()
198 EXPECT_EQ(F29, reg.AsOverlappingFpuRegister()); in TEST()
199 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W29))); in TEST()
279 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST() local
281 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
282 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
283 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
284 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
285 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
287 EXPECT_EQ(W0, reg.AsOverlappingVectorRegister()); in TEST()
288 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
289 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
290 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
291 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
292 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
293 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
294 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
295 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
297 reg = Mips64ManagedRegister::FromFpuRegister(F4); in TEST()
299 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
300 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
301 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
302 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
303 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
305 EXPECT_EQ(W4, reg.AsOverlappingVectorRegister()); in TEST()
306 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
307 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
308 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
309 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
310 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
311 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
312 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
313 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
315 reg = Mips64ManagedRegister::FromFpuRegister(F16); in TEST()
317 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
318 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
319 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
320 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
321 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
323 EXPECT_EQ(W16, reg.AsOverlappingVectorRegister()); in TEST()
324 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
325 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
326 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
327 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
328 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
329 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
330 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
331 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
333 reg = Mips64ManagedRegister::FromFpuRegister(F31); in TEST()
335 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
336 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
337 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
338 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
339 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
341 EXPECT_EQ(W31, reg.AsOverlappingVectorRegister()); in TEST()
342 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
343 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
344 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
345 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
346 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
347 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
348 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
349 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
351 reg = Mips64ManagedRegister::FromVectorRegister(W0); in TEST()
353 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
354 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
355 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
356 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
357 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
359 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister()); in TEST()
360 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
361 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
362 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
363 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
364 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
365 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
366 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
367 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
369 reg = Mips64ManagedRegister::FromVectorRegister(W4); in TEST()
371 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
372 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
373 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
374 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
375 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
377 EXPECT_EQ(F4, reg.AsOverlappingFpuRegister()); in TEST()
378 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
379 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
380 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
381 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
382 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
383 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
384 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
385 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
387 reg = Mips64ManagedRegister::FromVectorRegister(W16); in TEST()
389 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
390 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
391 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
392 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
393 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
395 EXPECT_EQ(F16, reg.AsOverlappingFpuRegister()); in TEST()
396 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
397 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
398 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
399 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
400 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
401 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
402 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
403 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
405 reg = Mips64ManagedRegister::FromVectorRegister(W31); in TEST()
407 EXPECT_TRUE(reg.Overlaps(reg_o)); in TEST()
408 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
409 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
410 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
411 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
413 EXPECT_EQ(F31, reg.AsOverlappingFpuRegister()); in TEST()
414 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
415 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
416 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
417 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
418 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
419 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
420 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
421 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
423 reg = Mips64ManagedRegister::FromGpuRegister(ZERO); in TEST()
424 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
425 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
426 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
427 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
428 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
429 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
430 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
431 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
432 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
433 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
434 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
435 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
437 reg = Mips64ManagedRegister::FromGpuRegister(A0); in TEST()
438 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
439 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
440 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
441 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
442 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
443 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
444 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
445 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
446 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
447 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
448 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
449 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
451 reg = Mips64ManagedRegister::FromGpuRegister(S0); in TEST()
452 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
453 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
454 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
455 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
456 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
457 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
458 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
459 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
460 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
461 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
462 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
463 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()
465 reg = Mips64ManagedRegister::FromGpuRegister(RA); in TEST()
466 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(ZERO))); in TEST()
467 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
468 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(S0))); in TEST()
469 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
470 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
471 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F4))); in TEST()
472 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F16))); in TEST()
473 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromFpuRegister(F31))); in TEST()
474 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W0))); in TEST()
475 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W4))); in TEST()
476 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16))); in TEST()
477 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W31))); in TEST()