55 #define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)  argument
56 #define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)  argument
57 #define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))  argument
259 #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \  argument
260 				 (devid) == PCI_CHIP_I915_GM || \
261 				 (devid) == PCI_CHIP_I945_GM || \
262 				 (devid) == PCI_CHIP_I945_GME || \
263 				 (devid) == PCI_CHIP_I965_GM || \
264 				 (devid) == PCI_CHIP_I965_GME || \
265 				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
266 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
267 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
269 #define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \  argument
270 				 (devid) == PCI_CHIP_Q45_G || \
271 				 (devid) == PCI_CHIP_G45_G || \
272 				 (devid) == PCI_CHIP_G41_G)
273 #define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)  argument
274 #define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))  argument
276 #define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)  argument
277 #define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)  argument
279 #define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \  argument
280 				 (devid) == PCI_CHIP_E7221_G || \
281 				 (devid) == PCI_CHIP_I915_GM)
283 #define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \  argument
284 				 (devid) == PCI_CHIP_I945_GME)
286 #define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \  argument
287 				 (devid) == PCI_CHIP_I945_GM || \
288 				 (devid) == PCI_CHIP_I945_GME || \
289 				 IS_G33(devid))
291 #define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \  argument
292 				 (devid) == PCI_CHIP_Q33_G || \
293 				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
295 #define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \  argument
296 				 (devid) == PCI_CHIP_845_G || \
297 				 (devid) == PCI_CHIP_I855_GM || \
298 				 (devid) == PCI_CHIP_I865_G)
300 #define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))  argument
302 #define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \  argument
303 				 (devid) == PCI_CHIP_I965_Q || \
304 				 (devid) == PCI_CHIP_I965_G_1 || \
305 				 (devid) == PCI_CHIP_I965_GM || \
306 				 (devid) == PCI_CHIP_I965_GME || \
307 				 (devid) == PCI_CHIP_I946_GZ || \
308 				 IS_G4X(devid))
310 #define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))  argument
312 #define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \  argument
313 				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
314 				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
315 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
316 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
317 				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
318 				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
320 #define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \  argument
321 				 IS_HASWELL(devid) || \
322 				 IS_VALLEYVIEW(devid))
324 #define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \  argument
325 				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
326 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
327 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
328 				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
329 				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
331 #define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \  argument
332 				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
333 				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
334 				 (devid) == PCI_CHIP_VALLEYVIEW_3)
336 #define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \  argument
337 				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
338 				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
339 				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
340 				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
341 				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
342 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
343 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
344 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
345 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
346 				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
347 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
348 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
349 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
350 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
351 				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
352 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
353 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
354 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
355 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
356 #define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \  argument
357 				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
358 				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
359 				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
360 				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
361 				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
362 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
363 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
364 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
365 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
366 				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
367 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
368 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
369 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
370 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
371 				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
372 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
373 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
374 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
375 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
376 #define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \  argument
377 				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
378 				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
379 				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
380 				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
381 				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
382 				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
383 				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
384 				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
385 				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
386 				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
387 				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
388 				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
389 				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
390 				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
391 				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
392 				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
393 				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
394 				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
395 				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
397 #define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \  argument
398 				 IS_HSW_GT2(devid) || \
399 				 IS_HSW_GT3(devid))
401 #define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \  argument
402 				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
403 				((devid & 0x000f) == BDW_SPARE) ? 1 : \
404 				((devid & 0x000f) == BDW_ULT) ? 1 : \
405 				((devid & 0x000f) == BDW_IRIS) ? 1 : \
406 				((devid & 0x000f) == BDW_SERVER) ? 1 : \
407 				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
408 				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
410 #define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \  argument
411 				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
412 				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
413 				 (devid) == PCI_CHIP_CHERRYVIEW_3)
415 #define IS_GEN8(devid)		(IS_BROADWELL(devid) || \  argument
416 				 IS_CHERRYVIEW(devid))
418 #define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \  argument
419 				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
420 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1	|| \
421 				 (devid) == PCI_CHIP_SKYLAKE_H_GT1	|| \
422 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
424 #define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \  argument
425 				 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2	|| \
426 				 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2	|| \
427 				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
428 				 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2	|| \
429 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
430 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
431 				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2	|| \
432 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
433 				 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
435 #define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0	|| \  argument
436 				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1	|| \
437 				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2	|| \
438 				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
439 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
441 #define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_SRV_GT4	|| \  argument
442 				 (devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \
443 				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X	|| \
444 				 (devid) == PCI_CHIP_SKYLAKE_H_GT4	|| \
445 				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
447 #define IS_KBL_GT1(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5	|| \  argument
448 				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5	|| \
449 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1	|| \
450 				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1	|| \
451 				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1	|| \
452 				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
453 				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
454 				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
456 #define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2	|| \  argument
457 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F	|| \
458 				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2	|| \
459 				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2	|| \
460 				 (devid) == PCI_CHIP_KABYLAKE_M_GT2	|| \
461 				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2	|| \
462 				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2	|| \
463 				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
465 #define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0	|| \  argument
466 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1	|| \
467 				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
469 #define IS_KBL_GT4(devid)	((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)  argument
471 #define IS_KABYLAKE(devid)	(IS_KBL_GT1(devid) || \  argument
472 				 IS_KBL_GT2(devid) || \
473 				 IS_KBL_GT3(devid) || \
474 				 IS_KBL_GT4(devid))
476 #define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \  argument
477 				 IS_SKL_GT2(devid) || \
478 				 IS_SKL_GT3(devid) || \
479 				 IS_SKL_GT4(devid))
481 #define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0	|| \  argument
482 				 (devid) == PCI_CHIP_BROXTON_1	|| \
483 				 (devid) == PCI_CHIP_BROXTON_2	|| \
484 				 (devid) == PCI_CHIP_BROXTON_3	|| \
485 				 (devid) == PCI_CHIP_BROXTON_4)
487 #define IS_GEMINILAKE(devid)	((devid) == PCI_CHIP_GLK || \  argument
488 				 (devid) == PCI_CHIP_GLK_2X6)
490 #define IS_CFL_S(devid)         ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \  argument
491                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
492                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
493                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
494                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
495                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
496                                  (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
498 #define IS_CFL_H(devid)         ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \  argument
499                                  (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
501 #define IS_CFL_U(devid)         ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \  argument
502                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
503                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
504                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
505                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
506                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
507                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
508                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
509                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
510                                  (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
512 #define IS_COFFEELAKE(devid)   (IS_CFL_S(devid) || \  argument
513 				IS_CFL_H(devid) || \
514 				IS_CFL_U(devid))
516 #define IS_GEN9(devid)		(IS_SKYLAKE(devid)  || \  argument
517 				 IS_BROXTON(devid)  || \
518 				 IS_KABYLAKE(devid) || \
519 				 IS_GEMINILAKE(devid) || \
520 				 IS_COFFEELAKE(devid))
522 #define IS_CANNONLAKE(devid)	((devid) == PCI_CHIP_CANNONLAKE_0 || \  argument
523 				 (devid) == PCI_CHIP_CANNONLAKE_1 || \
524 				 (devid) == PCI_CHIP_CANNONLAKE_2 || \
525 				 (devid) == PCI_CHIP_CANNONLAKE_3 || \
526 				 (devid) == PCI_CHIP_CANNONLAKE_4 || \
527 				 (devid) == PCI_CHIP_CANNONLAKE_5 || \
528 				 (devid) == PCI_CHIP_CANNONLAKE_6 || \
529 				 (devid) == PCI_CHIP_CANNONLAKE_7 || \
530 				 (devid) == PCI_CHIP_CANNONLAKE_8 || \
531 				 (devid) == PCI_CHIP_CANNONLAKE_9 || \
532 				 (devid) == PCI_CHIP_CANNONLAKE_10 || \
533 				 (devid) == PCI_CHIP_CANNONLAKE_11 || \
534 				 (devid) == PCI_CHIP_CANNONLAKE_12 || \
535 				 (devid) == PCI_CHIP_CANNONLAKE_13)
537 #define IS_GEN10(devid)		(IS_CANNONLAKE(devid))  argument