Lines Matching +full:gas +full:- +full:preprocessor
21 The backend of LLVM features a target-independent code generator that may
22 create output for several types of target CPUs --- including X86, PowerPC,
34 --------
40 --------------------
44 * `LLVM Language Reference Manual <LangRef.html>`_ --- a reference manual for
47 * :doc:`CodeGenerator` --- a guide to the components (classes and code
51 Formation, SSA-based Optimization, Register Allocation, Prolog/Epilog Code
54 * :doc:`TableGen/index` --- a document that describes the TableGen
55 (``tblgen``) application that manages domain-specific information to support
60 * :doc:`WritingAnLLVMPass` --- The assembly printer is a ``FunctionPass``, as
67 the GNU Assembler format (``GAS``), see `Using As
73 -----------
87 target-specific ``RegisterInfo.td`` input file. You should also write
93 for target-specific instructions from target-specific versions of
99 Graph (DAG) representation of instructions to native target-specific
101 selects instructions based on additional information in a target-specific
104 DAG-to-DAG instruction selection. Also write code in ``XXXISelLowering.cpp``
108 * Write code for an assembly printer that converts LLVM IR to a GAS format for
110 defined in your target-specific version of ``TargetInstrInfo.td``. You
112 LLVM-to-assembly conversion and a trivial subclass of ``TargetAsmInfo``.
116 ``TargetSubtarget`` class, which allows you to use the ``-mcpu=`` and
117 ``-mattr=`` command-line options.
127 -------------
131 target-independent code generator, you must perform the steps described in the
132 :doc:`LLVM Target-Independent Code Generator <CodeGenerator>` document.
146 Note that these two naming schemes are hardcoded into ``llvm-config``. Using
147 any other naming scheme will confuse ``llvm-config`` and produce a lot of
159 with ``-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=Dummy``. This will build your
169 the LLVM target-independent code generator. The ``LLVMTargetMachine`` class
174 numerous command-line options.
176 To create a concrete target-specific subclass of ``LLVMTargetMachine``, start
187 implement the ``getDataLayout`` method to access an object with target-specific
194 .. code-block:: c++
251 .. code-block:: c++
254 : DataLayout("E-p:32:32-f128:128:128"),
261 * An upper-case "``E``" in the string indicates a big-endian target data model.
262 A lower-case "``e``" indicates little-endian.
289 .. code-block:: c++
301 because some clients may wish to only link in some parts of the target --- the
305 .. code-block:: c++
312 </doxygen/TargetRegistry_8h-source.html>`_".
317 You should describe a concrete target-specific class that represents the
326 integer, floating-point, or vector registers. A register allocator allows an
330 target-independent register allocator automatically choose the actual
337 implementation of ``XXXRegisterInfo`` requires hand-coding.
340 -------------------
348 .. code-block:: llvm
364 .. code-block:: llvm
371 representing 3 different modes: the first element is for X86-64, the second for
372 exception handling (EH) on X86-32, and the third is generic. -1 is a special
373 Dwarf number that indicates the gcc number is undefined, and -2 indicates the
379 .. code-block:: c++
393 .. code-block:: c++
399 const unsigned *SubRegs; // Sub-register set
400 const unsigned *ImmSubRegs; // Immediate sub-register set
401 const unsigned *SuperRegs; // Super-register set
409 aliases for one another, so TableGen generates a null-terminated array
417 .. code-block:: llvm
425 and ``Rd``. SPARC registers are identified by 5-bit ID numbers, which is a
430 .. code-block:: llvm
436 // Ri - 32-bit integer registers
441 // Rf - 32-bit floating-point registers
446 // Rd - Slots in the FP register file for 64-bit floating-point values.
455 .. code-block:: llvm
466 The last two registers shown above (``D0`` and ``D1``) are double-precision
467 floating-point registers that are aliases for pairs of single-precision
468 floating-point sub-registers. In addition to aliases, the sub-register and
469 super-register relationships of the defined register are in fields of a
473 -------------------------
481 .. code-block:: llvm
510 floating-point types (``f32``, ``f64``), and vector types (for example,
513 different configurations. For example a register that can process a 128-bit
514 vector may be able to handle 16 8-bit integer elements, 8 16-bit integers, 4
515 32-bit integers, and so on.
531 defines a group of 32 single-precision floating-point registers (``F0`` to
532 ``F31``); ``DFPRegs`` defines a group of 16 double-precision registers
533 (``D0-D15``).
535 .. code-block:: llvm
549 // Non-allocatable regs:
574 .. code-block:: c++
596 // IntRegs Sub-register Classess...
601 // IntRegs Super-register Classess...
606 // IntRegs Register Class sub-classes...
611 // IntRegs Register Class super-classes...
627 ----------------------------------------------
635 * ``getCalleeSavedRegs`` --- Returns a list of callee-saved registers in the
636 order of the desired callee-save stack frame offset.
638 * ``getReservedRegs`` --- Returns a bitset indexed by physical register
641 * ``hasFP`` --- Return a Boolean indicating if a function should have a
644 * ``eliminateCallFramePseudoInstr`` --- If call frame setup or destroy pseudo
647 * ``eliminateFrameIndex`` --- Eliminate abstract frame indices from
650 * ``emitPrologue`` --- Insert prologue code into the function.
652 * ``emitEpilogue`` --- Insert epilogue code into the function.
654 .. _instruction-set:
670 * ``Target.td`` --- Where the ``Instruction``, ``Operand``, ``InstrInfo``, and
673 * ``TargetSelectionDAG.td`` --- Used by ``SelectionDAG`` instruction selection
679 * ``XXXInstrFormats.td`` --- Patterns for definitions of target-specific
682 * ``XXXInstrInfo.td`` --- Target-specific definitions of instruction templates,
688 There is also a target-specific ``XXX.td`` file, where ``XXX`` is the name of
692 You should describe a concrete target-specific class ``XXXInstrInfo`` that
700 * Target-independent properties (such as memory access, is commutable)
701 * Target-specific flags
706 .. code-block:: llvm
721 target-specific instruction that is defined in ``XXXInstrInfo.td``. The
740 major 32-bit formats for instructions. Format 1 is only for the ``CALL``
750 floating-point operations. ``SparcInstrInfo.td`` also adds the base class
763 .. code-block:: llvm
772 .. code-block:: llvm
783 This parameter is detailed in the next section, :ref:`instruction-selector`.
791 .. code-block:: llvm
804 .. code-block:: llvm
821 .. code-block:: llvm
833 .. code-block:: llvm
850 ---------------------------
858 .. code-block:: llvm
868 .. code-block:: llvm
874 let Inst{31-30} = op;
883 .. code-block:: llvm
891 let Inst{29-25} = rd;
892 let Inst{24-19} = op3;
893 let Inst{18-14} = rs1;
900 .. code-block:: llvm
909 let Inst{12-5} = asi; // address space identifier
910 let Inst{4-0} = rs2;
928 .. code-block:: llvm
933 int DIndex = SP::getNamedOperandIdx(SP::XNORrr, SP::OpName::d); // => -1
941 to define a few preprocessor macros in XXXInstrInfo.cpp and XXXInstrInfo.h.
946 .. code-block:: c++
953 .. code-block:: c++
975 .. code-block:: llvm
982 .. code-block:: c++
999 preprocessor macro:
1001 .. code-block:: c++
1008 ----------------------
1016 ----------------------------
1022 according to the target-specific instruction set. Relation models are defined
1030 -------------------------------------------
1038 * ``isLoadFromStackSlot`` --- If the specified machine instruction is a direct
1042 * ``isStoreToStackSlot`` --- If the specified machine instruction is a direct
1046 * ``copyPhysReg`` --- Copy values between a pair of physical registers.
1048 * ``storeRegToStackSlot`` --- Store a register value to a stack slot.
1050 * ``loadRegFromStackSlot`` --- Load a register value from a stack slot.
1052 * ``storeRegToAddr`` --- Store a register value to memory.
1054 * ``loadRegFromAddr`` --- Load a register value from memory.
1056 * ``foldMemoryOperand`` --- Attempt to combine instructions of any load or
1060 --------------------------------
1079 * ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
1081 * ``MachineBasicBlock *&TBB`` --- A destination block that is returned. For a
1084 * ``MachineBasicBlock *&FBB`` --- For a conditional branch that evaluates to
1087 * ``std::vector<MachineOperand> &Cond`` --- List of operands to evaluate a
1096 .. code-block:: c++
1104 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
1111 .. code-block:: c++
1114 TBB = LastInst->getOperand(0).getMBB();
1122 .. code-block:: c++
1126 TBB = SecondLastInst->getOperand(0).getMBB();
1128 I->eraseFromParent();
1138 .. code-block:: c++
1141 // Block ends with fall-through condbranch.
1142 TBB = LastInst->getOperand(0).getMBB();
1143 Cond.push_back(LastInst->getOperand(1));
1144 Cond.push_back(LastInst->getOperand(2));
1156 .. code-block:: c++
1158 unsigned SecondLastOpc = SecondLastInst->getOpcode();
1162 TBB = SecondLastInst->getOperand(0).getMBB();
1163 Cond.push_back(SecondLastInst->getOperand(1));
1164 Cond.push_back(SecondLastInst->getOperand(2));
1165 FBB = LastInst->getOperand(0).getMBB();
1182 .. _instruction-selector:
1189 generation, instruction selection passes are performed to convert non-native
1190 DAG instructions into native target-specific instructions. The pass described
1191 in ``XXXISelDAGToDAG.cpp`` is used to match patterns and perform DAG-to-DAG
1193 ``XXXBranchSelector.cpp``) to perform similar DAG-to-DAG operations for branch
1201 * ``XXXInstrInfo.td`` --- Contains definitions of instructions in a
1202 target-specific instruction set, generates ``XXXGenDAGISel.inc``, which is
1205 * ``XXXCallingConv.td`` --- Contains the calling and return value conventions
1217 :ref:`SelectionDAG-Process`.
1225 .. code-block:: llvm
1232 .. code-block:: llvm
1243 .. code-block:: llvm
1248 return !ST->isTruncatingStore() &&
1249 ST->getAddressingMode() == ISD::UNINDEXED;
1258 .. code-block:: c++
1262 MVT::ValueType NVT = N.getNode()->getValueType(0);
1279 .. code-block:: c++
1294 N1.getNode()->getValueType(0) == MVT::i32 &&
1295 N2.getNode()->getValueType(0) == MVT::i32) {
1301 -------------------------------
1305 need to add code to the target-specific ``XXXTargetLowering`` implementation to
1316 .. code-block:: c++
1329 * ``setOperationAction`` --- General operation.
1330 * ``setLoadExtAction`` --- Load with extension.
1331 * ``setTruncStoreAction`` --- Truncating store.
1332 * ``setIndexedLoadAction`` --- Indexed load.
1333 * ``setIndexedStoreAction`` --- Indexed store.
1334 * ``setConvertAction`` --- Type conversion.
1335 * ``setCondCodeAction`` --- Support for a given condition code.
1353 not support a sign-extending load for Boolean values (``i1`` type), so in
1357 .. code-block:: c++
1367 floating-point sine and cosine trig operations are supported by expansion to
1371 .. code-block:: c++
1390 .. code-block:: c++
1398 .. code-block:: c++
1408 convert the floating-point value to an integer.
1410 .. code-block:: c++
1426 non-v9 SPARC implementations.
1428 .. code-block:: c++
1436 -------------------
1438 To support target-specific calling conventions, ``XXXGenCallingConv.td`` uses
1461 .. code-block:: llvm
1465 ``SparcCallingConv.td`` contains definitions for a target-specific return-value
1466 calling convention (``RetCC_Sparc32``) and a basic 32-bit C calling convention
1468 which registers are used for specified scalar return types. A single-precision
1469 float is returned to register ``F0``, and a double-precision float goes to
1470 register ``D0``. A 32-bit integer is returned in register ``I0`` or ``I1``.
1472 .. code-block:: llvm
1484 alignment along 4-byte units. (Special cases: if size is zero, then the ABI
1487 .. code-block:: llvm
1496 specified sub-calling convention, and, if a match is found, it is invoked. In
1502 .. code-block:: llvm
1517 .. code-block:: llvm
1527 * ``CCIf <predicate, action>`` --- If the predicate matches, apply the action.
1529 * ``CCIfInReg <action>`` --- If the argument is marked with the "``inreg``"
1532 * ``CCIfNest <action>`` --- If the argument is marked with the "``nest``"
1535 * ``CCIfNotVarArg <action>`` --- If the current function does not take a
1538 * ``CCAssignToRegWithShadow <registerList, shadowList>`` --- similar to
1541 * ``CCPassByVal <size, align>`` --- Assign value to a stack slot with the
1544 * ``CCPromoteToType <type>`` --- Promote the current value to the specified
1547 * ``CallingConv <[actions]>`` --- Define each calling convention that is
1555 printer that converts LLVM IR to a GAS-format assembly language for your target
1560 :ref:`instruction-set`.) TableGen will produce an output file
1564 * Write ``XXXTargetAsmInfo.h``, which contains the bare-bones declaration of
1567 * Write ``XXXTargetAsmInfo.cpp``, which contains target-specific values for
1571 performs the LLVM-to-assembly conversion.
1579 .. code-block:: c++
1594 A target-specific implementation of ``AsmPrinter`` is written in
1601 .. code-block:: c++
1613 ``runOnMachineFunction``. Target-specific implementations of
1664 architecture: Version 8 (V8, which is a 32-bit architecture), Version 9 (V9, a
1665 64-bit architecture), and the UltraSPARC architecture. V8 has 16
1666 double-precision floating-point registers that are also usable as either 32
1667 single-precision or 8 quad-precision registers. V8 is also purely big-endian.
1668 V9 has 32 double-precision floating-point registers that are also usable as 16
1669 quad-precision registers, but cannot be used as single-precision registers.
1673 If subtarget support is needed, you should implement a target-specific
1675 command-line options ``-mcpu=`` and ``-mattr=``.
1685 .. code-block:: llvm
1699 .. code-block:: llvm
1702 "Enable SPARC-V9 instructions">;
1703 def FeatureV8Deprecated : SubtargetFeature<"deprecated-v8",
1713 .. code-block:: llvm
1730 def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
1737 should be included in the ``SparcSubtarget.cpp``. The target-specific
1740 .. code-block:: c++
1752 The implementation of a target machine optionally includes a Just-In-Time (JIT)
1758 that transforms target-machine instructions into relocatable machine
1762 target-specific code-generation activities, such as emitting machine code and
1782 --------------------
1784 In ``XXXCodeEmitter.cpp``, a target-specific of the ``Emitter`` class is
1786 target-specific implementation of ``runOnMachineFunction`` (invoked by
1794 .. code-block:: c++
1796 switch (Desc->TSFlags & X86::FormMask) {
1798 ... // or pseudo-instructions
1847 .. code-block:: c++
1880 for that target is defined in the short target-specific ``XXXRelocations.h``
1889 .. code-block:: c++
1899 ---------------
1901 ``XXXJITInfo.cpp`` implements the JIT interfaces for target-specific
1902 code-generation activities, such as emitting machine code and stubs. At
1903 minimum, a target-specific version of ``XXXJITInfo`` implements the following:
1905 * ``getLazyResolverFunction`` --- Initializes the JIT, gives the target a
1908 * ``emitFunctionStub`` --- Returns a native function with a specified address
1911 * ``relocate`` --- Changes the addresses of referenced globals, based on
1923 .. code-block:: c++
1937 function needs low-level access to the registers or stack, so it is typically