Lines Matching refs:FMUL
628 case ISD::FMUL: in isNegatibleForFree()
698 case ISD::FMUL: in GetNegatedExpression()
1406 case ISD::FMUL: return visitFMUL(N); in visit()
7795 if (Aggressive && N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7796 N1.getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7802 if (N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7810 if (N1.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7821 if (N00.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7833 if (N10.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7846 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7857 N1.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7881 if (N020.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7907 if (N002.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7920 if (N120.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7936 if (N102.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7981 if (N0.getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
7990 if (N1.getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
7999 N0.getOperand(0).getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
8014 if (N00.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8028 if (N10.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8048 if (N000.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8070 if (N000.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8089 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8102 N1.getOperand(2).getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8122 if (N020.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8145 if (N002.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8166 if (N120.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8193 if (N102.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8223 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMACombine()
8363 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) { in visitFADD()
8364 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
8372 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP, Flags); in visitFADD()
8381 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP, Flags); in visitFADD()
8385 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
8393 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP, Flags); in visitFADD()
8402 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP, Flags); in visitFADD()
8411 return DAG.getNode(ISD::FMUL, DL, VT, in visitFADD()
8421 return DAG.getNode(ISD::FMUL, DL, VT, in visitFADD()
8432 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), in visitFADD()
8530 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1, Flags); in visitFMUL()
8535 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0, Flags); in visitFMUL()
8547 if (N0.getOpcode() == ISD::FMUL) { in visitFMUL()
8564 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1, Flags); in visitFMUL()
8565 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts, Flags); in visitFMUL()
8578 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1, Flags); in visitFMUL()
8579 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts, Flags); in visitFMUL()
8598 return DAG.getNode(ISD::FMUL, DL, VT, in visitFMUL()
8655 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
8658 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8664 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
8669 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1), in visitFMA()
8694 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8702 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8764 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend, in combineRepeatedFPDivisors()
8811 return DAG.getNode(ISD::FMUL, DL, VT, N0, in visitFDIV()
8819 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8827 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8835 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8837 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
8855 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8863 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
9329 if (N0.getOpcode() == ISD::FMUL && in visitFNEG()
9338 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), in visitFNEG()
14547 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est, Flags); in BuildReciprocalEstimate()
14553 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); in BuildReciprocalEstimate()
14581 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags); in buildSqrtNROneConst()
14589 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags); in buildSqrtNROneConst()
14592 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags); in buildSqrtNROneConst()
14598 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); in buildSqrtNROneConst()
14604 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags); in buildSqrtNROneConst()
14631 SDValue AE = DAG.getNode(ISD::FMUL, DL, VT, Arg, Est, Flags); in buildSqrtNRTwoConst()
14634 SDValue AEE = DAG.getNode(ISD::FMUL, DL, VT, AE, Est, Flags); in buildSqrtNRTwoConst()
14646 LHS = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags); in buildSqrtNRTwoConst()
14649 LHS = DAG.getNode(ISD::FMUL, DL, VT, AE, MinusHalf, Flags); in buildSqrtNRTwoConst()
14653 Est = DAG.getNode(ISD::FMUL, DL, VT, LHS, RHS, Flags); in buildSqrtNRTwoConst()