289     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());  in getVR()  local
292     if (!VReg) {  in getVR()
295       VReg = MRI->createVirtualRegister(RC);  in getVR()
298             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);  in getVR()
299     return VReg;  in getVR()
322   unsigned VReg = getVR(Op, VRBaseMap);  in AddRegisterOperand()  local
336     assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) &&  in AddRegisterOperand()
338     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {  in AddRegisterOperand()
341               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);  in AddRegisterOperand()
342       VReg = NewVReg;  in AddRegisterOperand()
368   MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |  in AddRegisterOperand()
444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,  in ConstrainForSubReg()  argument
446   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);  in ConstrainForSubReg()
452     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);  in ConstrainForSubReg()
456     return VReg;  in ConstrainForSubReg()
464     .addReg(VReg);  in ConstrainForSubReg()
497     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);  in EmitSubregNode()  local
498     MachineInstr *DefMI = MRI->getVRegDef(VReg);  in EmitSubregNode()
517       VReg = ConstrainForSubReg(VReg, SubIdx,  in EmitSubregNode()
527               TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);  in EmitSubregNode()
590   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);  in EmitCopyToRegClassNode()  local
598     NewVReg).addReg(VReg);  in EmitCopyToRegClassNode()