1114     SUnit *SuccSU = Succ.getSUnit();  in CopyAndMoveSuccessors()  local
1115     if (SuccSU->isScheduled) {  in CopyAndMoveSuccessors()
1118       AddPred(SuccSU, D);  in CopyAndMoveSuccessors()
1120       DelDeps.push_back(std::make_pair(SuccSU, D));  in CopyAndMoveSuccessors()
1153     SUnit *SuccSU = Succ.getSUnit();  in InsertCopiesAndMoveSuccs()  local
1154     if (SuccSU->isScheduled) {  in InsertCopiesAndMoveSuccs()
1157       AddPred(SuccSU, D);  in InsertCopiesAndMoveSuccs()
1158       DelDeps.push_back(std::make_pair(SuccSU, Succ));  in InsertCopiesAndMoveSuccs()
1164       AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial));  in InsertCopiesAndMoveSuccs()
2240     const SUnit *SuccSU = Succ.getSUnit();  in hasOnlyLiveOutUses()  local
2241     if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {  in hasOnlyLiveOutUses()
2243         cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveOutUses()
2704     SUnit *SuccSU = Succ.getSUnit();  in canClobberReachingPhysRegUse()  local
2705     for (const SDep &SuccPred : SuccSU->Preds) {  in canClobberReachingPhysRegUse()
2729 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,  in canClobberPhysRegDefs()  argument
2732   SDNode *N = SuccSU->getNode();  in canClobberPhysRegDefs()
2865       SUnit *SuccSU = Edge.getSUnit();  in PrescheduleNodesWithMultipleUses()  local
2866       if (SuccSU != &SU) {  in PrescheduleNodesWithMultipleUses()
2868         scheduleDAG->RemovePred(SuccSU, Edge);  in PrescheduleNodesWithMultipleUses()
2871         scheduleDAG->AddPred(SuccSU, Edge);  in PrescheduleNodesWithMultipleUses()
2912         SUnit *SuccSU = Succ.getSUnit();  in AddPseudoTwoAddrDeps()  local
2913         if (SuccSU == &SU)  in AddPseudoTwoAddrDeps()
2917         if (SuccSU->getHeight() < SU.getHeight() &&  in AddPseudoTwoAddrDeps()
2918             (SU.getHeight() - SuccSU->getHeight()) > 1)  in AddPseudoTwoAddrDeps()
2924         while (SuccSU->Succs.size() == 1 &&  in AddPseudoTwoAddrDeps()
2925                SuccSU->getNode()->isMachineOpcode() &&  in AddPseudoTwoAddrDeps()
2926                SuccSU->getNode()->getMachineOpcode() ==  in AddPseudoTwoAddrDeps()
2928           SuccSU = SuccSU->Succs.front().getSUnit();  in AddPseudoTwoAddrDeps()
2930         if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())  in AddPseudoTwoAddrDeps()
2934         if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) {  in AddPseudoTwoAddrDeps()
2935           if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI))  in AddPseudoTwoAddrDeps()
2940         unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();  in AddPseudoTwoAddrDeps()
2945         if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) &&  in AddPseudoTwoAddrDeps()
2946             (!canClobber(SuccSU, DUSU) ||  in AddPseudoTwoAddrDeps()
2947              (isLiveOut && !hasOnlyLiveOutUses(SuccSU)) ||  in AddPseudoTwoAddrDeps()
2948              (!SU.isCommutable && SuccSU->isCommutable)) &&  in AddPseudoTwoAddrDeps()
2949             !scheduleDAG->IsReachable(SuccSU, &SU)) {  in AddPseudoTwoAddrDeps()
2951                        << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n");  in AddPseudoTwoAddrDeps()
2952           scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial));  in AddPseudoTwoAddrDeps()