155   MachineInstr *CmpMI;  member in __anon2dd089570111::SSACCmpConv
185   bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
378                                      const MachineInstr *CmpMI) {  in canSpeculateInstrs()  argument
422     if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {  in canSpeculateInstrs()
549   CmpMI = findConvertibleCompare(CmpBB);  in canConvert()
550   if (!CmpMI)  in canConvert()
553   if (!canSpeculateInstrs(CmpBB, CmpMI)) {  in canConvert()
612   switch (CmpMI->getOpcode()) {  in convert()
648   MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),  in convert()
650   if (CmpMI->getOperand(FirstOp + 1).isReg())  in convert()
651     MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),  in convert()
654       BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)  in convert()
655           .addOperand(CmpMI->getOperand(FirstOp)); // Register Rn  in convert()
659     MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate  in convert()
665     bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||  in convert()
666                 CmpMI->getOpcode() == AArch64::CBNZX;  in convert()
667     BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))  in convert()
669         .addOperand(CmpMI->getOperand(1)); // Branch target.  in convert()
671   CmpMI->eraseFromParent();  in convert()
702   switch (CmpMI->getOpcode()) {  in expectedCodeSizeDelta()