162                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
165                          bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
168                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
173                          bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
182   bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
197   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
206                             bool LHSIsKill, uint64_t Imm);
208                             bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
210   unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
1128   bool LHSIsKill = hasTrivialKill(LHS);  in emitAddSub()  local
1137       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,  in emitAddSub()
1140       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,  in emitAddSub()
1144       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,  in emitAddSub()
1160           return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1168     return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1188       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1213           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1231   return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitAddSub()
1236                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rr()  argument
1264       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rr()
1270                                         bool LHSIsKill, uint64_t Imm,  in emitAddSub_ri()  argument
1308       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_ri()
1315                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rs()  argument
1349       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rs()
1356                                         bool LHSIsKill, unsigned RHSReg,  in emitAddSub_rx()  argument
1392       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitAddSub_rx()
1426 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitICmp_ri()  argument
1428   return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,  in emitICmp_ri()
1446   bool LHSIsKill = hasTrivialKill(LHS);  in emitFCmp()  local
1451         .addReg(LHSReg, getKillRegState(LHSIsKill));  in emitFCmp()
1462       .addReg(LHSReg, getKillRegState(LHSIsKill))  in emitFCmp()
1504                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rr()  argument
1506   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rr()
1511                                       bool LHSIsKill, unsigned RHSReg,  in emitSubs_rs()  argument
1515   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitSubs_rs()
1540   bool LHSIsKill = hasTrivialKill(LHS);  in emitLogicalOp()  local
1545     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1567       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1583         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1596   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1605                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_ri()  argument
1641       fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,  in emitLogicalOp_ri()
1651                                            unsigned LHSReg, bool LHSIsKill,  in emitLogicalOp_rs()  argument
1684       fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,  in emitLogicalOp_rs()
1693 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,  in emitAnd_ri()  argument
1695   return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);  in emitAnd_ri()
3585       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3593         MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3608         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()
3620       bool LHSIsKill = hasTrivialKill(LHS);  in fastLowerIntrinsicCall()  local
3628         MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in fastLowerIntrinsicCall()
3640         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,  in fastLowerIntrinsicCall()