218                       unsigned Op1Reg, bool Op1IsKill);
222                       unsigned Op1Reg, bool Op1IsKill);
226                       unsigned Op1Reg, bool Op1IsKill);
3909                                      unsigned Op1Reg, bool Op1IsKill) {  in emitLSL_rr()  argument
3924     Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);  in emitLSL_rr()
3927   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSL_rr()
4015                                      unsigned Op1Reg, bool Op1IsKill) {  in emitLSR_rr()  argument
4031     Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);  in emitLSR_rr()
4034   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSR_rr()
4136                                      unsigned Op1Reg, bool Op1IsKill) {  in emitASR_rr()  argument
4152     Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);  in emitASR_rr()
4155   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitASR_rr()
4642   unsigned Op1Reg = getRegForValue(I->getOperand(1));  in selectShift()  local
4643   if (!Op1Reg)  in selectShift()
4651     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4654     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4657     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()