Lines Matching refs:AArch64
36 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), in AArch64InstrInfo()
46 if (MI.getOpcode() == AArch64::INLINEASM) in GetInstSizeInBytes()
70 case AArch64::Bcc: in parseCondBranch()
74 case AArch64::CBZW: in parseCondBranch()
75 case AArch64::CBZX: in parseCondBranch()
76 case AArch64::CBNZW: in parseCondBranch()
77 case AArch64::CBNZX: in parseCondBranch()
83 case AArch64::TBZW: in parseCondBranch()
84 case AArch64::TBZX: in parseCondBranch()
85 case AArch64::TBNZW: in parseCondBranch()
86 case AArch64::TBNZX: in parseCondBranch()
194 case AArch64::CBZW: in ReverseBranchCondition()
195 Cond[1].setImm(AArch64::CBNZW); in ReverseBranchCondition()
197 case AArch64::CBNZW: in ReverseBranchCondition()
198 Cond[1].setImm(AArch64::CBZW); in ReverseBranchCondition()
200 case AArch64::CBZX: in ReverseBranchCondition()
201 Cond[1].setImm(AArch64::CBNZX); in ReverseBranchCondition()
203 case AArch64::CBNZX: in ReverseBranchCondition()
204 Cond[1].setImm(AArch64::CBZX); in ReverseBranchCondition()
206 case AArch64::TBZW: in ReverseBranchCondition()
207 Cond[1].setImm(AArch64::TBNZW); in ReverseBranchCondition()
209 case AArch64::TBNZW: in ReverseBranchCondition()
210 Cond[1].setImm(AArch64::TBZW); in ReverseBranchCondition()
212 case AArch64::TBZX: in ReverseBranchCondition()
213 Cond[1].setImm(AArch64::TBNZX); in ReverseBranchCondition()
215 case AArch64::TBNZX: in ReverseBranchCondition()
216 Cond[1].setImm(AArch64::TBZX); in ReverseBranchCondition()
254 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); in instantiateCondBranch()
276 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB); in InsertBranch()
284 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB); in InsertBranch()
308 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
313 case AArch64::ADDSXri: in canFoldIntoCSel()
314 case AArch64::ADDSWri: in canFoldIntoCSel()
316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
319 case AArch64::ADDXri: in canFoldIntoCSel()
320 case AArch64::ADDWri: in canFoldIntoCSel()
326 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
329 case AArch64::ORNXrr: in canFoldIntoCSel()
330 case AArch64::ORNWrr: { in canFoldIntoCSel()
333 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
336 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
340 case AArch64::SUBSXrr: in canFoldIntoCSel()
341 case AArch64::SUBSWrr: in canFoldIntoCSel()
343 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
346 case AArch64::SUBXrr: in canFoldIntoCSel()
347 case AArch64::SUBWrr: { in canFoldIntoCSel()
350 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
353 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
382 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
383 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
396 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
397 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
428 case AArch64::CBZW: in insertSelect()
432 case AArch64::CBZX: in insertSelect()
436 case AArch64::CBNZW: in insertSelect()
440 case AArch64::CBNZX: in insertSelect()
448 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
449 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR) in insertSelect()
454 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
455 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR) in insertSelect()
467 case AArch64::TBZW: in insertSelect()
468 case AArch64::TBZX: in insertSelect()
471 case AArch64::TBNZW: in insertSelect()
472 case AArch64::TBNZX: in insertSelect()
477 if (Cond[1].getImm() == AArch64::TBZW || Cond[1].getImm() == AArch64::TBNZW) in insertSelect()
478 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR) in insertSelect()
483 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR) in insertSelect()
494 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
495 RC = &AArch64::GPR64RegClass; in insertSelect()
496 Opc = AArch64::CSELXr; in insertSelect()
498 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
499 RC = &AArch64::GPR32RegClass; in insertSelect()
500 Opc = AArch64::CSELWr; in insertSelect()
502 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
503 RC = &AArch64::FPR64RegClass; in insertSelect()
504 Opc = AArch64::FCSELDrrr; in insertSelect()
505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
506 RC = &AArch64::FPR32RegClass; in insertSelect()
507 Opc = AArch64::FCSELSrrr; in insertSelect()
562 case AArch64::ADDWri: in isAsCheapAsAMove()
563 case AArch64::ADDXri: in isAsCheapAsAMove()
564 case AArch64::SUBWri: in isAsCheapAsAMove()
565 case AArch64::SUBXri: in isAsCheapAsAMove()
570 case AArch64::ADDWrs: in isAsCheapAsAMove()
571 case AArch64::ADDXrs: in isAsCheapAsAMove()
572 case AArch64::SUBWrs: in isAsCheapAsAMove()
573 case AArch64::SUBXrs: in isAsCheapAsAMove()
579 case AArch64::ANDWri: in isAsCheapAsAMove()
580 case AArch64::ANDXri: in isAsCheapAsAMove()
581 case AArch64::EORWri: in isAsCheapAsAMove()
582 case AArch64::EORXri: in isAsCheapAsAMove()
583 case AArch64::ORRWri: in isAsCheapAsAMove()
584 case AArch64::ORRXri: in isAsCheapAsAMove()
588 case AArch64::ANDWrr: in isAsCheapAsAMove()
589 case AArch64::ANDXrr: in isAsCheapAsAMove()
590 case AArch64::BICWrr: in isAsCheapAsAMove()
591 case AArch64::BICXrr: in isAsCheapAsAMove()
592 case AArch64::EONWrr: in isAsCheapAsAMove()
593 case AArch64::EONXrr: in isAsCheapAsAMove()
594 case AArch64::EORWrr: in isAsCheapAsAMove()
595 case AArch64::EORXrr: in isAsCheapAsAMove()
596 case AArch64::ORNWrr: in isAsCheapAsAMove()
597 case AArch64::ORNXrr: in isAsCheapAsAMove()
598 case AArch64::ORRWrr: in isAsCheapAsAMove()
599 case AArch64::ORRXrr: in isAsCheapAsAMove()
603 case AArch64::ANDWrs: in isAsCheapAsAMove()
604 case AArch64::ANDXrs: in isAsCheapAsAMove()
605 case AArch64::BICWrs: in isAsCheapAsAMove()
606 case AArch64::BICXrs: in isAsCheapAsAMove()
607 case AArch64::EONWrs: in isAsCheapAsAMove()
608 case AArch64::EONXrs: in isAsCheapAsAMove()
609 case AArch64::EORWrs: in isAsCheapAsAMove()
610 case AArch64::EORXrs: in isAsCheapAsAMove()
611 case AArch64::ORNWrs: in isAsCheapAsAMove()
612 case AArch64::ORNXrs: in isAsCheapAsAMove()
613 case AArch64::ORRWrs: in isAsCheapAsAMove()
614 case AArch64::ORRXrs: in isAsCheapAsAMove()
622 case AArch64::MOVi32imm: in isAsCheapAsAMove()
624 case AArch64::MOVi64imm: in isAsCheapAsAMove()
629 case AArch64::FMOVS0: in isAsCheapAsAMove()
630 case AArch64::FMOVD0: in isAsCheapAsAMove()
643 case AArch64::SBFMXri: // aka sxtw in isCoalescableExtInstr()
644 case AArch64::UBFMXri: // aka uxtw in isCoalescableExtInstr()
652 SubIdx = AArch64::sub_32; in isCoalescableExtInstr()
698 case AArch64::SUBSWrr: in analyzeCompare()
699 case AArch64::SUBSWrs: in analyzeCompare()
700 case AArch64::SUBSWrx: in analyzeCompare()
701 case AArch64::SUBSXrr: in analyzeCompare()
702 case AArch64::SUBSXrs: in analyzeCompare()
703 case AArch64::SUBSXrx: in analyzeCompare()
704 case AArch64::ADDSWrr: in analyzeCompare()
705 case AArch64::ADDSWrs: in analyzeCompare()
706 case AArch64::ADDSWrx: in analyzeCompare()
707 case AArch64::ADDSXrr: in analyzeCompare()
708 case AArch64::ADDSXrs: in analyzeCompare()
709 case AArch64::ADDSXrx: in analyzeCompare()
716 case AArch64::SUBSWri: in analyzeCompare()
717 case AArch64::ADDSWri: in analyzeCompare()
718 case AArch64::SUBSXri: in analyzeCompare()
719 case AArch64::ADDSXri: in analyzeCompare()
726 case AArch64::ANDSWri: in analyzeCompare()
727 case AArch64::ANDSXri: in analyzeCompare()
740 MI.getOpcode() == AArch64::ANDSWri ? 32 : 64) != 0; in analyzeCompare()
792 if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR)) in convertFlagSettingOpcode()
798 case AArch64::ADDSWrr: in convertFlagSettingOpcode()
799 return AArch64::ADDWrr; in convertFlagSettingOpcode()
800 case AArch64::ADDSWri: in convertFlagSettingOpcode()
801 return MIDefinesZeroReg ? AArch64::ADDSWri : AArch64::ADDWri; in convertFlagSettingOpcode()
802 case AArch64::ADDSWrs: in convertFlagSettingOpcode()
803 return MIDefinesZeroReg ? AArch64::ADDSWrs : AArch64::ADDWrs; in convertFlagSettingOpcode()
804 case AArch64::ADDSWrx: in convertFlagSettingOpcode()
805 return AArch64::ADDWrx; in convertFlagSettingOpcode()
806 case AArch64::ADDSXrr: in convertFlagSettingOpcode()
807 return AArch64::ADDXrr; in convertFlagSettingOpcode()
808 case AArch64::ADDSXri: in convertFlagSettingOpcode()
809 return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri; in convertFlagSettingOpcode()
810 case AArch64::ADDSXrs: in convertFlagSettingOpcode()
811 return MIDefinesZeroReg ? AArch64::ADDSXrs : AArch64::ADDXrs; in convertFlagSettingOpcode()
812 case AArch64::ADDSXrx: in convertFlagSettingOpcode()
813 return AArch64::ADDXrx; in convertFlagSettingOpcode()
814 case AArch64::SUBSWrr: in convertFlagSettingOpcode()
815 return AArch64::SUBWrr; in convertFlagSettingOpcode()
816 case AArch64::SUBSWri: in convertFlagSettingOpcode()
817 return MIDefinesZeroReg ? AArch64::SUBSWri : AArch64::SUBWri; in convertFlagSettingOpcode()
818 case AArch64::SUBSWrs: in convertFlagSettingOpcode()
819 return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs; in convertFlagSettingOpcode()
820 case AArch64::SUBSWrx: in convertFlagSettingOpcode()
821 return AArch64::SUBWrx; in convertFlagSettingOpcode()
822 case AArch64::SUBSXrr: in convertFlagSettingOpcode()
823 return AArch64::SUBXrr; in convertFlagSettingOpcode()
824 case AArch64::SUBSXri: in convertFlagSettingOpcode()
825 return MIDefinesZeroReg ? AArch64::SUBSXri : AArch64::SUBXri; in convertFlagSettingOpcode()
826 case AArch64::SUBSXrs: in convertFlagSettingOpcode()
827 return MIDefinesZeroReg ? AArch64::SUBSXrs : AArch64::SUBXrs; in convertFlagSettingOpcode()
828 case AArch64::SUBSXrx: in convertFlagSettingOpcode()
829 return AArch64::SUBXrx; in convertFlagSettingOpcode()
866 if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) || in areCFlagsAccessedBetweenInstrs()
867 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI))) in areCFlagsAccessedBetweenInstrs()
889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
891 if (CmpInstr.definesRegister(AArch64::WZR) || in optimizeCompareInstr()
892 CmpInstr.definesRegister(AArch64::XZR)) { in optimizeCompareInstr()
930 return AArch64::INSTRUCTION_LIST_END; in sForm()
932 case AArch64::ADDSWrr: in sForm()
933 case AArch64::ADDSWri: in sForm()
934 case AArch64::ADDSXrr: in sForm()
935 case AArch64::ADDSXri: in sForm()
936 case AArch64::SUBSWrr: in sForm()
937 case AArch64::SUBSWri: in sForm()
938 case AArch64::SUBSXrr: in sForm()
939 case AArch64::SUBSXri: in sForm()
942 case AArch64::ADDWrr: return AArch64::ADDSWrr; in sForm()
943 case AArch64::ADDWri: return AArch64::ADDSWri; in sForm()
944 case AArch64::ADDXrr: return AArch64::ADDSXrr; in sForm()
945 case AArch64::ADDXri: return AArch64::ADDSXri; in sForm()
946 case AArch64::ADCWr: return AArch64::ADCSWr; in sForm()
947 case AArch64::ADCXr: return AArch64::ADCSXr; in sForm()
948 case AArch64::SUBWrr: return AArch64::SUBSWrr; in sForm()
949 case AArch64::SUBWri: return AArch64::SUBSWri; in sForm()
950 case AArch64::SUBXrr: return AArch64::SUBSXrr; in sForm()
951 case AArch64::SUBXri: return AArch64::SUBSXri; in sForm()
952 case AArch64::SBCWr: return AArch64::SBCSWr; in sForm()
953 case AArch64::SBCXr: return AArch64::SBCSXr; in sForm()
954 case AArch64::ANDWri: return AArch64::ANDSWri; in sForm()
955 case AArch64::ANDXri: return AArch64::ANDSXri; in sForm()
962 if (BB->isLiveIn(AArch64::NZCV)) in areCFlagsAliveInSuccessors()
990 case AArch64::Bcc: { in findCondCodeUsedByInstr()
991 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
996 case AArch64::CSINVWr: in findCondCodeUsedByInstr()
997 case AArch64::CSINVXr: in findCondCodeUsedByInstr()
998 case AArch64::CSINCWr: in findCondCodeUsedByInstr()
999 case AArch64::CSINCXr: in findCondCodeUsedByInstr()
1000 case AArch64::CSELWr: in findCondCodeUsedByInstr()
1001 case AArch64::CSELXr: in findCondCodeUsedByInstr()
1002 case AArch64::CSNEGWr: in findCondCodeUsedByInstr()
1003 case AArch64::CSNEGXr: in findCondCodeUsedByInstr()
1004 case AArch64::FCSELSrrr: in findCondCodeUsedByInstr()
1005 case AArch64::FCSELDrrr: { in findCondCodeUsedByInstr()
1006 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
1056 return Opcode == AArch64::ADDSWri || Opcode == AArch64::ADDSXri; in isADDSRegImm()
1060 return Opcode == AArch64::SUBSWri || Opcode == AArch64::SUBSXri; in isSUBSRegImm()
1077 assert(sForm(*MI) != AArch64::INSTRUCTION_LIST_END); in canInstrSubstituteCmpInstr()
1100 if (Instr.readsRegister(AArch64::NZCV, TRI)) { in canInstrSubstituteCmpInstr()
1107 if (Instr.modifiesRegister(AArch64::NZCV, TRI)) in canInstrSubstituteCmpInstr()
1130 if (NewOpc == AArch64::INSTRUCTION_LIST_END) in substituteCmpToZero()
1142 MI->addRegisterDefined(AArch64::NZCV, TRI); in substituteCmpToZero()
1160 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg) in expandPostRAPseudo()
1162 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) in expandPostRAPseudo()
1167 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg) in expandPostRAPseudo()
1169 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) in expandPostRAPseudo()
1172 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) in expandPostRAPseudo()
1175 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg) in expandPostRAPseudo()
1178 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) in expandPostRAPseudo()
1183 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg) in expandPostRAPseudo()
1186 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg) in expandPostRAPseudo()
1202 case AArch64::ADDSWrs: in hasShiftedReg()
1203 case AArch64::ADDSXrs: in hasShiftedReg()
1204 case AArch64::ADDWrs: in hasShiftedReg()
1205 case AArch64::ADDXrs: in hasShiftedReg()
1206 case AArch64::ANDSWrs: in hasShiftedReg()
1207 case AArch64::ANDSXrs: in hasShiftedReg()
1208 case AArch64::ANDWrs: in hasShiftedReg()
1209 case AArch64::ANDXrs: in hasShiftedReg()
1210 case AArch64::BICSWrs: in hasShiftedReg()
1211 case AArch64::BICSXrs: in hasShiftedReg()
1212 case AArch64::BICWrs: in hasShiftedReg()
1213 case AArch64::BICXrs: in hasShiftedReg()
1214 case AArch64::CRC32Brr: in hasShiftedReg()
1215 case AArch64::CRC32CBrr: in hasShiftedReg()
1216 case AArch64::CRC32CHrr: in hasShiftedReg()
1217 case AArch64::CRC32CWrr: in hasShiftedReg()
1218 case AArch64::CRC32CXrr: in hasShiftedReg()
1219 case AArch64::CRC32Hrr: in hasShiftedReg()
1220 case AArch64::CRC32Wrr: in hasShiftedReg()
1221 case AArch64::CRC32Xrr: in hasShiftedReg()
1222 case AArch64::EONWrs: in hasShiftedReg()
1223 case AArch64::EONXrs: in hasShiftedReg()
1224 case AArch64::EORWrs: in hasShiftedReg()
1225 case AArch64::EORXrs: in hasShiftedReg()
1226 case AArch64::ORNWrs: in hasShiftedReg()
1227 case AArch64::ORNXrs: in hasShiftedReg()
1228 case AArch64::ORRWrs: in hasShiftedReg()
1229 case AArch64::ORRXrs: in hasShiftedReg()
1230 case AArch64::SUBSWrs: in hasShiftedReg()
1231 case AArch64::SUBSXrs: in hasShiftedReg()
1232 case AArch64::SUBWrs: in hasShiftedReg()
1233 case AArch64::SUBXrs: in hasShiftedReg()
1248 case AArch64::ADDSWrx: in hasExtendedReg()
1249 case AArch64::ADDSXrx: in hasExtendedReg()
1250 case AArch64::ADDSXrx64: in hasExtendedReg()
1251 case AArch64::ADDWrx: in hasExtendedReg()
1252 case AArch64::ADDXrx: in hasExtendedReg()
1253 case AArch64::ADDXrx64: in hasExtendedReg()
1254 case AArch64::SUBSWrx: in hasExtendedReg()
1255 case AArch64::SUBSXrx: in hasExtendedReg()
1256 case AArch64::SUBSXrx64: in hasExtendedReg()
1257 case AArch64::SUBWrx: in hasExtendedReg()
1258 case AArch64::SUBXrx: in hasExtendedReg()
1259 case AArch64::SUBXrx64: in hasExtendedReg()
1276 case AArch64::MOVZWi: in isGPRZero()
1277 case AArch64::MOVZXi: // movz Rd, #0 (LSL #0) in isGPRZero()
1284 case AArch64::ANDWri: // and Rd, Rzr, #imm in isGPRZero()
1285 return MI.getOperand(1).getReg() == AArch64::WZR; in isGPRZero()
1286 case AArch64::ANDXri: in isGPRZero()
1287 return MI.getOperand(1).getReg() == AArch64::XZR; in isGPRZero()
1289 return MI.getOperand(1).getReg() == AArch64::WZR; in isGPRZero()
1303 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
1304 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()
1306 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0) in isGPRCopy()
1307 if (MI.getOperand(1).getReg() == AArch64::XZR) { in isGPRCopy()
1313 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0) in isGPRCopy()
1333 return (AArch64::FPR64RegClass.contains(DstReg) || in isFPRCopy()
1334 AArch64::FPR128RegClass.contains(DstReg)); in isFPRCopy()
1336 case AArch64::ORRv16i8: in isFPRCopy()
1352 case AArch64::LDRWui: in isLoadFromStackSlot()
1353 case AArch64::LDRXui: in isLoadFromStackSlot()
1354 case AArch64::LDRBui: in isLoadFromStackSlot()
1355 case AArch64::LDRHui: in isLoadFromStackSlot()
1356 case AArch64::LDRSui: in isLoadFromStackSlot()
1357 case AArch64::LDRDui: in isLoadFromStackSlot()
1358 case AArch64::LDRQui: in isLoadFromStackSlot()
1375 case AArch64::STRWui: in isStoreToStackSlot()
1376 case AArch64::STRXui: in isStoreToStackSlot()
1377 case AArch64::STRBui: in isStoreToStackSlot()
1378 case AArch64::STRHui: in isStoreToStackSlot()
1379 case AArch64::STRSui: in isStoreToStackSlot()
1380 case AArch64::STRDui: in isStoreToStackSlot()
1381 case AArch64::STRQui: in isStoreToStackSlot()
1399 case AArch64::LDRBBroW: in isScaledAddr()
1400 case AArch64::LDRBroW: in isScaledAddr()
1401 case AArch64::LDRDroW: in isScaledAddr()
1402 case AArch64::LDRHHroW: in isScaledAddr()
1403 case AArch64::LDRHroW: in isScaledAddr()
1404 case AArch64::LDRQroW: in isScaledAddr()
1405 case AArch64::LDRSBWroW: in isScaledAddr()
1406 case AArch64::LDRSBXroW: in isScaledAddr()
1407 case AArch64::LDRSHWroW: in isScaledAddr()
1408 case AArch64::LDRSHXroW: in isScaledAddr()
1409 case AArch64::LDRSWroW: in isScaledAddr()
1410 case AArch64::LDRSroW: in isScaledAddr()
1411 case AArch64::LDRWroW: in isScaledAddr()
1412 case AArch64::LDRXroW: in isScaledAddr()
1413 case AArch64::STRBBroW: in isScaledAddr()
1414 case AArch64::STRBroW: in isScaledAddr()
1415 case AArch64::STRDroW: in isScaledAddr()
1416 case AArch64::STRHHroW: in isScaledAddr()
1417 case AArch64::STRHroW: in isScaledAddr()
1418 case AArch64::STRQroW: in isScaledAddr()
1419 case AArch64::STRSroW: in isScaledAddr()
1420 case AArch64::STRWroW: in isScaledAddr()
1421 case AArch64::STRXroW: in isScaledAddr()
1422 case AArch64::LDRBBroX: in isScaledAddr()
1423 case AArch64::LDRBroX: in isScaledAddr()
1424 case AArch64::LDRDroX: in isScaledAddr()
1425 case AArch64::LDRHHroX: in isScaledAddr()
1426 case AArch64::LDRHroX: in isScaledAddr()
1427 case AArch64::LDRQroX: in isScaledAddr()
1428 case AArch64::LDRSBWroX: in isScaledAddr()
1429 case AArch64::LDRSBXroX: in isScaledAddr()
1430 case AArch64::LDRSHWroX: in isScaledAddr()
1431 case AArch64::LDRSHXroX: in isScaledAddr()
1432 case AArch64::LDRSWroX: in isScaledAddr()
1433 case AArch64::LDRSroX: in isScaledAddr()
1434 case AArch64::LDRWroX: in isScaledAddr()
1435 case AArch64::LDRXroX: in isScaledAddr()
1436 case AArch64::STRBBroX: in isScaledAddr()
1437 case AArch64::STRBroX: in isScaledAddr()
1438 case AArch64::STRDroX: in isScaledAddr()
1439 case AArch64::STRHHroX: in isScaledAddr()
1440 case AArch64::STRHroX: in isScaledAddr()
1441 case AArch64::STRQroX: in isScaledAddr()
1442 case AArch64::STRSroX: in isScaledAddr()
1443 case AArch64::STRWroX: in isScaledAddr()
1444 case AArch64::STRXroX: in isScaledAddr()
1471 case AArch64::STURSi: in isUnscaledLdSt()
1472 case AArch64::STURDi: in isUnscaledLdSt()
1473 case AArch64::STURQi: in isUnscaledLdSt()
1474 case AArch64::STURBBi: in isUnscaledLdSt()
1475 case AArch64::STURHHi: in isUnscaledLdSt()
1476 case AArch64::STURWi: in isUnscaledLdSt()
1477 case AArch64::STURXi: in isUnscaledLdSt()
1478 case AArch64::LDURSi: in isUnscaledLdSt()
1479 case AArch64::LDURDi: in isUnscaledLdSt()
1480 case AArch64::LDURQi: in isUnscaledLdSt()
1481 case AArch64::LDURWi: in isUnscaledLdSt()
1482 case AArch64::LDURXi: in isUnscaledLdSt()
1483 case AArch64::LDURSWi: in isUnscaledLdSt()
1484 case AArch64::LDURHHi: in isUnscaledLdSt()
1485 case AArch64::LDURBBi: in isUnscaledLdSt()
1486 case AArch64::LDURSBWi: in isUnscaledLdSt()
1487 case AArch64::LDURSHWi: in isUnscaledLdSt()
1526 case AArch64::LDURQi: in isCandidateToMergeOrPair()
1527 case AArch64::STURQi: in isCandidateToMergeOrPair()
1528 case AArch64::LDRQui: in isCandidateToMergeOrPair()
1529 case AArch64::STRQui: in isCandidateToMergeOrPair()
1544 case AArch64::STRSui: in getMemOpBaseRegImmOfs()
1545 case AArch64::STRDui: in getMemOpBaseRegImmOfs()
1546 case AArch64::STRQui: in getMemOpBaseRegImmOfs()
1547 case AArch64::STRXui: in getMemOpBaseRegImmOfs()
1548 case AArch64::STRWui: in getMemOpBaseRegImmOfs()
1549 case AArch64::LDRSui: in getMemOpBaseRegImmOfs()
1550 case AArch64::LDRDui: in getMemOpBaseRegImmOfs()
1551 case AArch64::LDRQui: in getMemOpBaseRegImmOfs()
1552 case AArch64::LDRXui: in getMemOpBaseRegImmOfs()
1553 case AArch64::LDRWui: in getMemOpBaseRegImmOfs()
1554 case AArch64::LDRSWui: in getMemOpBaseRegImmOfs()
1556 case AArch64::STURSi: in getMemOpBaseRegImmOfs()
1557 case AArch64::STURDi: in getMemOpBaseRegImmOfs()
1558 case AArch64::STURQi: in getMemOpBaseRegImmOfs()
1559 case AArch64::STURXi: in getMemOpBaseRegImmOfs()
1560 case AArch64::STURWi: in getMemOpBaseRegImmOfs()
1561 case AArch64::LDURSi: in getMemOpBaseRegImmOfs()
1562 case AArch64::LDURDi: in getMemOpBaseRegImmOfs()
1563 case AArch64::LDURQi: in getMemOpBaseRegImmOfs()
1564 case AArch64::LDURWi: in getMemOpBaseRegImmOfs()
1565 case AArch64::LDURXi: in getMemOpBaseRegImmOfs()
1566 case AArch64::LDURSWi: in getMemOpBaseRegImmOfs()
1595 case AArch64::LDURQi: in getMemOpBaseRegImmOfsWidth()
1596 case AArch64::STURQi: in getMemOpBaseRegImmOfsWidth()
1600 case AArch64::LDURXi: in getMemOpBaseRegImmOfsWidth()
1601 case AArch64::LDURDi: in getMemOpBaseRegImmOfsWidth()
1602 case AArch64::STURXi: in getMemOpBaseRegImmOfsWidth()
1603 case AArch64::STURDi: in getMemOpBaseRegImmOfsWidth()
1607 case AArch64::LDURWi: in getMemOpBaseRegImmOfsWidth()
1608 case AArch64::LDURSi: in getMemOpBaseRegImmOfsWidth()
1609 case AArch64::LDURSWi: in getMemOpBaseRegImmOfsWidth()
1610 case AArch64::STURWi: in getMemOpBaseRegImmOfsWidth()
1611 case AArch64::STURSi: in getMemOpBaseRegImmOfsWidth()
1615 case AArch64::LDURHi: in getMemOpBaseRegImmOfsWidth()
1616 case AArch64::LDURHHi: in getMemOpBaseRegImmOfsWidth()
1617 case AArch64::LDURSHXi: in getMemOpBaseRegImmOfsWidth()
1618 case AArch64::LDURSHWi: in getMemOpBaseRegImmOfsWidth()
1619 case AArch64::STURHi: in getMemOpBaseRegImmOfsWidth()
1620 case AArch64::STURHHi: in getMemOpBaseRegImmOfsWidth()
1624 case AArch64::LDURBi: in getMemOpBaseRegImmOfsWidth()
1625 case AArch64::LDURBBi: in getMemOpBaseRegImmOfsWidth()
1626 case AArch64::LDURSBXi: in getMemOpBaseRegImmOfsWidth()
1627 case AArch64::LDURSBWi: in getMemOpBaseRegImmOfsWidth()
1628 case AArch64::STURBi: in getMemOpBaseRegImmOfsWidth()
1629 case AArch64::STURBBi: in getMemOpBaseRegImmOfsWidth()
1633 case AArch64::LDPQi: in getMemOpBaseRegImmOfsWidth()
1634 case AArch64::LDNPQi: in getMemOpBaseRegImmOfsWidth()
1635 case AArch64::STPQi: in getMemOpBaseRegImmOfsWidth()
1636 case AArch64::STNPQi: in getMemOpBaseRegImmOfsWidth()
1640 case AArch64::LDRQui: in getMemOpBaseRegImmOfsWidth()
1641 case AArch64::STRQui: in getMemOpBaseRegImmOfsWidth()
1644 case AArch64::LDPXi: in getMemOpBaseRegImmOfsWidth()
1645 case AArch64::LDPDi: in getMemOpBaseRegImmOfsWidth()
1646 case AArch64::LDNPXi: in getMemOpBaseRegImmOfsWidth()
1647 case AArch64::LDNPDi: in getMemOpBaseRegImmOfsWidth()
1648 case AArch64::STPXi: in getMemOpBaseRegImmOfsWidth()
1649 case AArch64::STPDi: in getMemOpBaseRegImmOfsWidth()
1650 case AArch64::STNPXi: in getMemOpBaseRegImmOfsWidth()
1651 case AArch64::STNPDi: in getMemOpBaseRegImmOfsWidth()
1655 case AArch64::LDRXui: in getMemOpBaseRegImmOfsWidth()
1656 case AArch64::LDRDui: in getMemOpBaseRegImmOfsWidth()
1657 case AArch64::STRXui: in getMemOpBaseRegImmOfsWidth()
1658 case AArch64::STRDui: in getMemOpBaseRegImmOfsWidth()
1661 case AArch64::LDPWi: in getMemOpBaseRegImmOfsWidth()
1662 case AArch64::LDPSi: in getMemOpBaseRegImmOfsWidth()
1663 case AArch64::LDNPWi: in getMemOpBaseRegImmOfsWidth()
1664 case AArch64::LDNPSi: in getMemOpBaseRegImmOfsWidth()
1665 case AArch64::STPWi: in getMemOpBaseRegImmOfsWidth()
1666 case AArch64::STPSi: in getMemOpBaseRegImmOfsWidth()
1667 case AArch64::STNPWi: in getMemOpBaseRegImmOfsWidth()
1668 case AArch64::STNPSi: in getMemOpBaseRegImmOfsWidth()
1672 case AArch64::LDRWui: in getMemOpBaseRegImmOfsWidth()
1673 case AArch64::LDRSui: in getMemOpBaseRegImmOfsWidth()
1674 case AArch64::LDRSWui: in getMemOpBaseRegImmOfsWidth()
1675 case AArch64::STRWui: in getMemOpBaseRegImmOfsWidth()
1676 case AArch64::STRSui: in getMemOpBaseRegImmOfsWidth()
1679 case AArch64::LDRHui: in getMemOpBaseRegImmOfsWidth()
1680 case AArch64::LDRHHui: in getMemOpBaseRegImmOfsWidth()
1681 case AArch64::STRHui: in getMemOpBaseRegImmOfsWidth()
1682 case AArch64::STRHHui: in getMemOpBaseRegImmOfsWidth()
1685 case AArch64::LDRBui: in getMemOpBaseRegImmOfsWidth()
1686 case AArch64::LDRBBui: in getMemOpBaseRegImmOfsWidth()
1687 case AArch64::STRBui: in getMemOpBaseRegImmOfsWidth()
1688 case AArch64::STRBBui: in getMemOpBaseRegImmOfsWidth()
1711 case AArch64::LDURQi: in scaleOffset()
1712 case AArch64::STURQi: in scaleOffset()
1715 case AArch64::LDURXi: in scaleOffset()
1716 case AArch64::LDURDi: in scaleOffset()
1717 case AArch64::STURXi: in scaleOffset()
1718 case AArch64::STURDi: in scaleOffset()
1721 case AArch64::LDURWi: in scaleOffset()
1722 case AArch64::LDURSi: in scaleOffset()
1723 case AArch64::LDURSWi: in scaleOffset()
1724 case AArch64::STURWi: in scaleOffset()
1725 case AArch64::STURSi: in scaleOffset()
1747 case AArch64::LDRWui: in canPairLdStOpc()
1748 case AArch64::LDURWi: in canPairLdStOpc()
1749 return SecondOpc == AArch64::LDRSWui || SecondOpc == AArch64::LDURSWi; in canPairLdStOpc()
1750 case AArch64::LDRSWui: in canPairLdStOpc()
1751 case AArch64::LDURSWi: in canPairLdStOpc()
1752 return SecondOpc == AArch64::LDRWui || SecondOpc == AArch64::LDURWi; in canPairLdStOpc()
1803 if (SecondOpcode == AArch64::Bcc) { in shouldScheduleAdjacent()
1807 case AArch64::SUBSWri: in shouldScheduleAdjacent()
1808 case AArch64::ADDSWri: in shouldScheduleAdjacent()
1809 case AArch64::ANDSWri: in shouldScheduleAdjacent()
1810 case AArch64::SUBSXri: in shouldScheduleAdjacent()
1811 case AArch64::ADDSXri: in shouldScheduleAdjacent()
1812 case AArch64::ANDSXri: in shouldScheduleAdjacent()
1817 if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX || in shouldScheduleAdjacent()
1818 SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) { in shouldScheduleAdjacent()
1822 case AArch64::ADDWri: in shouldScheduleAdjacent()
1823 case AArch64::ADDXri: in shouldScheduleAdjacent()
1824 case AArch64::ANDWri: in shouldScheduleAdjacent()
1825 case AArch64::ANDXri: in shouldScheduleAdjacent()
1826 case AArch64::EORWri: in shouldScheduleAdjacent()
1827 case AArch64::EORXri: in shouldScheduleAdjacent()
1828 case AArch64::ORRWri: in shouldScheduleAdjacent()
1829 case AArch64::ORRXri: in shouldScheduleAdjacent()
1830 case AArch64::SUBWri: in shouldScheduleAdjacent()
1831 case AArch64::SUBXri: in shouldScheduleAdjacent()
1842 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) in emitFrameIndexDebugValue()
1900 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
1901 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) { in copyPhysReg()
1904 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
1908 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
1909 &AArch64::GPR64spRegClass); in copyPhysReg()
1910 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, in copyPhysReg()
1911 &AArch64::GPR64spRegClass); in copyPhysReg()
1916 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX) in copyPhysReg()
1922 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
1927 } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) { in copyPhysReg()
1928 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm( in copyPhysReg()
1933 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
1934 &AArch64::GPR64spRegClass); in copyPhysReg()
1935 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32, in copyPhysReg()
1936 &AArch64::GPR64spRegClass); in copyPhysReg()
1941 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX) in copyPhysReg()
1942 .addReg(AArch64::XZR) in copyPhysReg()
1947 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg) in copyPhysReg()
1948 .addReg(AArch64::WZR) in copyPhysReg()
1955 if (AArch64::GPR64spRegClass.contains(DestReg) && in copyPhysReg()
1956 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) { in copyPhysReg()
1957 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { in copyPhysReg()
1959 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) in copyPhysReg()
1963 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) { in copyPhysReg()
1964 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm( in copyPhysReg()
1968 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) in copyPhysReg()
1969 .addReg(AArch64::XZR) in copyPhysReg()
1976 if (AArch64::DDDDRegClass.contains(DestReg) && in copyPhysReg()
1977 AArch64::DDDDRegClass.contains(SrcReg)) { in copyPhysReg()
1978 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1, in copyPhysReg()
1979 AArch64::dsub2, AArch64::dsub3 }; in copyPhysReg()
1980 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
1986 if (AArch64::DDDRegClass.contains(DestReg) && in copyPhysReg()
1987 AArch64::DDDRegClass.contains(SrcReg)) { in copyPhysReg()
1988 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1, in copyPhysReg()
1989 AArch64::dsub2 }; in copyPhysReg()
1990 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
1996 if (AArch64::DDRegClass.contains(DestReg) && in copyPhysReg()
1997 AArch64::DDRegClass.contains(SrcReg)) { in copyPhysReg()
1998 static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 }; in copyPhysReg()
1999 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
2005 if (AArch64::QQQQRegClass.contains(DestReg) && in copyPhysReg()
2006 AArch64::QQQQRegClass.contains(SrcReg)) { in copyPhysReg()
2007 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1, in copyPhysReg()
2008 AArch64::qsub2, AArch64::qsub3 }; in copyPhysReg()
2009 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2015 if (AArch64::QQQRegClass.contains(DestReg) && in copyPhysReg()
2016 AArch64::QQQRegClass.contains(SrcReg)) { in copyPhysReg()
2017 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1, in copyPhysReg()
2018 AArch64::qsub2 }; in copyPhysReg()
2019 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2025 if (AArch64::QQRegClass.contains(DestReg) && in copyPhysReg()
2026 AArch64::QQRegClass.contains(SrcReg)) { in copyPhysReg()
2027 static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 }; in copyPhysReg()
2028 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2033 if (AArch64::FPR128RegClass.contains(DestReg) && in copyPhysReg()
2034 AArch64::FPR128RegClass.contains(SrcReg)) { in copyPhysReg()
2036 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2040 BuildMI(MBB, I, DL, get(AArch64::STRQpre)) in copyPhysReg()
2041 .addReg(AArch64::SP, RegState::Define) in copyPhysReg()
2043 .addReg(AArch64::SP) in copyPhysReg()
2045 BuildMI(MBB, I, DL, get(AArch64::LDRQpre)) in copyPhysReg()
2046 .addReg(AArch64::SP, RegState::Define) in copyPhysReg()
2048 .addReg(AArch64::SP) in copyPhysReg()
2054 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
2055 AArch64::FPR64RegClass.contains(SrcReg)) { in copyPhysReg()
2057 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
2058 &AArch64::FPR128RegClass); in copyPhysReg()
2059 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub, in copyPhysReg()
2060 &AArch64::FPR128RegClass); in copyPhysReg()
2061 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2065 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg) in copyPhysReg()
2071 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
2072 AArch64::FPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2074 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
2075 &AArch64::FPR128RegClass); in copyPhysReg()
2076 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub, in copyPhysReg()
2077 &AArch64::FPR128RegClass); in copyPhysReg()
2078 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2082 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2088 if (AArch64::FPR16RegClass.contains(DestReg) && in copyPhysReg()
2089 AArch64::FPR16RegClass.contains(SrcReg)) { in copyPhysReg()
2091 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2092 &AArch64::FPR128RegClass); in copyPhysReg()
2093 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
2094 &AArch64::FPR128RegClass); in copyPhysReg()
2095 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2099 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2100 &AArch64::FPR32RegClass); in copyPhysReg()
2101 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
2102 &AArch64::FPR32RegClass); in copyPhysReg()
2103 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2109 if (AArch64::FPR8RegClass.contains(DestReg) && in copyPhysReg()
2110 AArch64::FPR8RegClass.contains(SrcReg)) { in copyPhysReg()
2112 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2113 &AArch64::FPR128RegClass); in copyPhysReg()
2114 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, in copyPhysReg()
2115 &AArch64::FPR128RegClass); in copyPhysReg()
2116 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2120 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2121 &AArch64::FPR32RegClass); in copyPhysReg()
2122 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub, in copyPhysReg()
2123 &AArch64::FPR32RegClass); in copyPhysReg()
2124 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2131 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
2132 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
2133 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg) in copyPhysReg()
2137 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
2138 AArch64::FPR64RegClass.contains(SrcReg)) { in copyPhysReg()
2139 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg) in copyPhysReg()
2144 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
2145 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2146 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg) in copyPhysReg()
2150 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
2151 AArch64::FPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2152 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg) in copyPhysReg()
2157 if (DestReg == AArch64::NZCV) { in copyPhysReg()
2158 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()
2159 BuildMI(MBB, I, DL, get(AArch64::MSR)) in copyPhysReg()
2162 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define); in copyPhysReg()
2166 if (SrcReg == AArch64::NZCV) { in copyPhysReg()
2167 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
2168 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg) in copyPhysReg()
2170 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
2195 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2196 Opc = AArch64::STRBui; in storeRegToStackSlot()
2199 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2200 Opc = AArch64::STRHui; in storeRegToStackSlot()
2203 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2204 Opc = AArch64::STRWui; in storeRegToStackSlot()
2206 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
2208 assert(SrcReg != AArch64::WSP); in storeRegToStackSlot()
2209 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2210 Opc = AArch64::STRSui; in storeRegToStackSlot()
2213 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2214 Opc = AArch64::STRXui; in storeRegToStackSlot()
2216 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
2218 assert(SrcReg != AArch64::SP); in storeRegToStackSlot()
2219 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2220 Opc = AArch64::STRDui; in storeRegToStackSlot()
2223 if (AArch64::FPR128RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
2224 Opc = AArch64::STRQui; in storeRegToStackSlot()
2225 else if (AArch64::DDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2228 Opc = AArch64::ST1Twov1d; in storeRegToStackSlot()
2233 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2236 Opc = AArch64::ST1Threev1d; in storeRegToStackSlot()
2241 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2244 Opc = AArch64::ST1Fourv1d; in storeRegToStackSlot()
2246 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2249 Opc = AArch64::ST1Twov2d; in storeRegToStackSlot()
2254 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2257 Opc = AArch64::ST1Threev2d; in storeRegToStackSlot()
2262 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
2265 Opc = AArch64::ST1Fourv2d; in storeRegToStackSlot()
2299 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2300 Opc = AArch64::LDRBui; in loadRegFromStackSlot()
2303 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2304 Opc = AArch64::LDRHui; in loadRegFromStackSlot()
2307 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2308 Opc = AArch64::LDRWui; in loadRegFromStackSlot()
2310 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2312 assert(DestReg != AArch64::WSP); in loadRegFromStackSlot()
2313 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2314 Opc = AArch64::LDRSui; in loadRegFromStackSlot()
2317 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2318 Opc = AArch64::LDRXui; in loadRegFromStackSlot()
2320 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2322 assert(DestReg != AArch64::SP); in loadRegFromStackSlot()
2323 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2324 Opc = AArch64::LDRDui; in loadRegFromStackSlot()
2327 if (AArch64::FPR128RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
2328 Opc = AArch64::LDRQui; in loadRegFromStackSlot()
2329 else if (AArch64::DDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2332 Opc = AArch64::LD1Twov1d; in loadRegFromStackSlot()
2337 if (AArch64::DDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2340 Opc = AArch64::LD1Threev1d; in loadRegFromStackSlot()
2345 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2348 Opc = AArch64::LD1Fourv1d; in loadRegFromStackSlot()
2350 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2353 Opc = AArch64::LD1Twov2d; in loadRegFromStackSlot()
2358 if (AArch64::QQQRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2361 Opc = AArch64::LD1Threev2d; in loadRegFromStackSlot()
2366 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
2369 Opc = AArch64::LD1Fourv2d; in loadRegFromStackSlot()
2392 assert((DestReg != AArch64::SP || Offset % 16 == 0) && in emitFrameOffset()
2412 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri; in emitFrameOffset()
2414 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri; in emitFrameOffset()
2465 if (SrcReg == AArch64::SP && in foldMemoryOperandImpl()
2467 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2470 if (DstReg == AArch64::SP && in foldMemoryOperandImpl()
2472 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2501 case AArch64::LD1Twov2d: in isAArch64FrameOffsetLegal()
2502 case AArch64::LD1Threev2d: in isAArch64FrameOffsetLegal()
2503 case AArch64::LD1Fourv2d: in isAArch64FrameOffsetLegal()
2504 case AArch64::LD1Twov1d: in isAArch64FrameOffsetLegal()
2505 case AArch64::LD1Threev1d: in isAArch64FrameOffsetLegal()
2506 case AArch64::LD1Fourv1d: in isAArch64FrameOffsetLegal()
2507 case AArch64::ST1Twov2d: in isAArch64FrameOffsetLegal()
2508 case AArch64::ST1Threev2d: in isAArch64FrameOffsetLegal()
2509 case AArch64::ST1Fourv2d: in isAArch64FrameOffsetLegal()
2510 case AArch64::ST1Twov1d: in isAArch64FrameOffsetLegal()
2511 case AArch64::ST1Threev1d: in isAArch64FrameOffsetLegal()
2512 case AArch64::ST1Fourv1d: in isAArch64FrameOffsetLegal()
2514 case AArch64::PRFMui: in isAArch64FrameOffsetLegal()
2516 UnscaledOp = AArch64::PRFUMi; in isAArch64FrameOffsetLegal()
2518 case AArch64::LDRXui: in isAArch64FrameOffsetLegal()
2520 UnscaledOp = AArch64::LDURXi; in isAArch64FrameOffsetLegal()
2522 case AArch64::LDRWui: in isAArch64FrameOffsetLegal()
2524 UnscaledOp = AArch64::LDURWi; in isAArch64FrameOffsetLegal()
2526 case AArch64::LDRBui: in isAArch64FrameOffsetLegal()
2528 UnscaledOp = AArch64::LDURBi; in isAArch64FrameOffsetLegal()
2530 case AArch64::LDRHui: in isAArch64FrameOffsetLegal()
2532 UnscaledOp = AArch64::LDURHi; in isAArch64FrameOffsetLegal()
2534 case AArch64::LDRSui: in isAArch64FrameOffsetLegal()
2536 UnscaledOp = AArch64::LDURSi; in isAArch64FrameOffsetLegal()
2538 case AArch64::LDRDui: in isAArch64FrameOffsetLegal()
2540 UnscaledOp = AArch64::LDURDi; in isAArch64FrameOffsetLegal()
2542 case AArch64::LDRQui: in isAArch64FrameOffsetLegal()
2544 UnscaledOp = AArch64::LDURQi; in isAArch64FrameOffsetLegal()
2546 case AArch64::LDRBBui: in isAArch64FrameOffsetLegal()
2548 UnscaledOp = AArch64::LDURBBi; in isAArch64FrameOffsetLegal()
2550 case AArch64::LDRHHui: in isAArch64FrameOffsetLegal()
2552 UnscaledOp = AArch64::LDURHHi; in isAArch64FrameOffsetLegal()
2554 case AArch64::LDRSBXui: in isAArch64FrameOffsetLegal()
2556 UnscaledOp = AArch64::LDURSBXi; in isAArch64FrameOffsetLegal()
2558 case AArch64::LDRSBWui: in isAArch64FrameOffsetLegal()
2560 UnscaledOp = AArch64::LDURSBWi; in isAArch64FrameOffsetLegal()
2562 case AArch64::LDRSHXui: in isAArch64FrameOffsetLegal()
2564 UnscaledOp = AArch64::LDURSHXi; in isAArch64FrameOffsetLegal()
2566 case AArch64::LDRSHWui: in isAArch64FrameOffsetLegal()
2568 UnscaledOp = AArch64::LDURSHWi; in isAArch64FrameOffsetLegal()
2570 case AArch64::LDRSWui: in isAArch64FrameOffsetLegal()
2572 UnscaledOp = AArch64::LDURSWi; in isAArch64FrameOffsetLegal()
2575 case AArch64::STRXui: in isAArch64FrameOffsetLegal()
2577 UnscaledOp = AArch64::STURXi; in isAArch64FrameOffsetLegal()
2579 case AArch64::STRWui: in isAArch64FrameOffsetLegal()
2581 UnscaledOp = AArch64::STURWi; in isAArch64FrameOffsetLegal()
2583 case AArch64::STRBui: in isAArch64FrameOffsetLegal()
2585 UnscaledOp = AArch64::STURBi; in isAArch64FrameOffsetLegal()
2587 case AArch64::STRHui: in isAArch64FrameOffsetLegal()
2589 UnscaledOp = AArch64::STURHi; in isAArch64FrameOffsetLegal()
2591 case AArch64::STRSui: in isAArch64FrameOffsetLegal()
2593 UnscaledOp = AArch64::STURSi; in isAArch64FrameOffsetLegal()
2595 case AArch64::STRDui: in isAArch64FrameOffsetLegal()
2597 UnscaledOp = AArch64::STURDi; in isAArch64FrameOffsetLegal()
2599 case AArch64::STRQui: in isAArch64FrameOffsetLegal()
2601 UnscaledOp = AArch64::STURQi; in isAArch64FrameOffsetLegal()
2603 case AArch64::STRBBui: in isAArch64FrameOffsetLegal()
2605 UnscaledOp = AArch64::STURBBi; in isAArch64FrameOffsetLegal()
2607 case AArch64::STRHHui: in isAArch64FrameOffsetLegal()
2609 UnscaledOp = AArch64::STURHHi; in isAArch64FrameOffsetLegal()
2612 case AArch64::LDPXi: in isAArch64FrameOffsetLegal()
2613 case AArch64::LDPDi: in isAArch64FrameOffsetLegal()
2614 case AArch64::STPXi: in isAArch64FrameOffsetLegal()
2615 case AArch64::STPDi: in isAArch64FrameOffsetLegal()
2616 case AArch64::LDNPXi: in isAArch64FrameOffsetLegal()
2617 case AArch64::LDNPDi: in isAArch64FrameOffsetLegal()
2618 case AArch64::STNPXi: in isAArch64FrameOffsetLegal()
2619 case AArch64::STNPDi: in isAArch64FrameOffsetLegal()
2624 case AArch64::LDPQi: in isAArch64FrameOffsetLegal()
2625 case AArch64::STPQi: in isAArch64FrameOffsetLegal()
2626 case AArch64::LDNPQi: in isAArch64FrameOffsetLegal()
2627 case AArch64::STNPQi: in isAArch64FrameOffsetLegal()
2632 case AArch64::LDPWi: in isAArch64FrameOffsetLegal()
2633 case AArch64::LDPSi: in isAArch64FrameOffsetLegal()
2634 case AArch64::STPWi: in isAArch64FrameOffsetLegal()
2635 case AArch64::STPSi: in isAArch64FrameOffsetLegal()
2636 case AArch64::LDNPWi: in isAArch64FrameOffsetLegal()
2637 case AArch64::LDNPSi: in isAArch64FrameOffsetLegal()
2638 case AArch64::STNPWi: in isAArch64FrameOffsetLegal()
2639 case AArch64::STNPSi: in isAArch64FrameOffsetLegal()
2645 case AArch64::LDURXi: in isAArch64FrameOffsetLegal()
2646 case AArch64::LDURWi: in isAArch64FrameOffsetLegal()
2647 case AArch64::LDURBi: in isAArch64FrameOffsetLegal()
2648 case AArch64::LDURHi: in isAArch64FrameOffsetLegal()
2649 case AArch64::LDURSi: in isAArch64FrameOffsetLegal()
2650 case AArch64::LDURDi: in isAArch64FrameOffsetLegal()
2651 case AArch64::LDURQi: in isAArch64FrameOffsetLegal()
2652 case AArch64::LDURHHi: in isAArch64FrameOffsetLegal()
2653 case AArch64::LDURBBi: in isAArch64FrameOffsetLegal()
2654 case AArch64::LDURSBXi: in isAArch64FrameOffsetLegal()
2655 case AArch64::LDURSBWi: in isAArch64FrameOffsetLegal()
2656 case AArch64::LDURSHXi: in isAArch64FrameOffsetLegal()
2657 case AArch64::LDURSHWi: in isAArch64FrameOffsetLegal()
2658 case AArch64::LDURSWi: in isAArch64FrameOffsetLegal()
2659 case AArch64::STURXi: in isAArch64FrameOffsetLegal()
2660 case AArch64::STURWi: in isAArch64FrameOffsetLegal()
2661 case AArch64::STURBi: in isAArch64FrameOffsetLegal()
2662 case AArch64::STURHi: in isAArch64FrameOffsetLegal()
2663 case AArch64::STURSi: in isAArch64FrameOffsetLegal()
2664 case AArch64::STURDi: in isAArch64FrameOffsetLegal()
2665 case AArch64::STURQi: in isAArch64FrameOffsetLegal()
2666 case AArch64::STURBBi: in isAArch64FrameOffsetLegal()
2667 case AArch64::STURHHi: in isAArch64FrameOffsetLegal()
2725 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) { in rewriteAArch64FrameIndex()
2729 MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri)); in rewriteAArch64FrameIndex()
2755 NopInst.setOpcode(AArch64::HINT); in getNoopForMachoTarget()
2768 case AArch64::ADDSWrr: in isCombineInstrSettingFlag()
2769 case AArch64::ADDSWri: in isCombineInstrSettingFlag()
2770 case AArch64::ADDSXrr: in isCombineInstrSettingFlag()
2771 case AArch64::ADDSXri: in isCombineInstrSettingFlag()
2772 case AArch64::SUBSWrr: in isCombineInstrSettingFlag()
2773 case AArch64::SUBSXrr: in isCombineInstrSettingFlag()
2775 case AArch64::SUBSWri: in isCombineInstrSettingFlag()
2776 case AArch64::SUBSXri: in isCombineInstrSettingFlag()
2787 case AArch64::ADDWrr: in isCombineInstrCandidate32()
2788 case AArch64::ADDWri: in isCombineInstrCandidate32()
2789 case AArch64::SUBWrr: in isCombineInstrCandidate32()
2790 case AArch64::ADDSWrr: in isCombineInstrCandidate32()
2791 case AArch64::ADDSWri: in isCombineInstrCandidate32()
2792 case AArch64::SUBSWrr: in isCombineInstrCandidate32()
2794 case AArch64::SUBWri: in isCombineInstrCandidate32()
2795 case AArch64::SUBSWri: in isCombineInstrCandidate32()
2806 case AArch64::ADDXrr: in isCombineInstrCandidate64()
2807 case AArch64::ADDXri: in isCombineInstrCandidate64()
2808 case AArch64::SUBXrr: in isCombineInstrCandidate64()
2809 case AArch64::ADDSXrr: in isCombineInstrCandidate64()
2810 case AArch64::ADDSXri: in isCombineInstrCandidate64()
2811 case AArch64::SUBSXrr: in isCombineInstrCandidate64()
2813 case AArch64::SUBXri: in isCombineInstrCandidate64()
2814 case AArch64::SUBSXri: in isCombineInstrCandidate64()
2825 case AArch64::FADDSrr: in isCombineInstrCandidateFP()
2826 case AArch64::FADDDrr: in isCombineInstrCandidateFP()
2827 case AArch64::FADDv2f32: in isCombineInstrCandidateFP()
2828 case AArch64::FADDv2f64: in isCombineInstrCandidateFP()
2829 case AArch64::FADDv4f32: in isCombineInstrCandidateFP()
2830 case AArch64::FSUBSrr: in isCombineInstrCandidateFP()
2831 case AArch64::FSUBDrr: in isCombineInstrCandidateFP()
2832 case AArch64::FSUBv2f32: in isCombineInstrCandidateFP()
2833 case AArch64::FSUBv2f64: in isCombineInstrCandidateFP()
2834 case AArch64::FSUBv4f32: in isCombineInstrCandidateFP()
2897 case AArch64::FADDDrr: in isAssociativeAndCommutative()
2898 case AArch64::FADDSrr: in isAssociativeAndCommutative()
2899 case AArch64::FADDv2f32: in isAssociativeAndCommutative()
2900 case AArch64::FADDv2f64: in isAssociativeAndCommutative()
2901 case AArch64::FADDv4f32: in isAssociativeAndCommutative()
2902 case AArch64::FMULDrr: in isAssociativeAndCommutative()
2903 case AArch64::FMULSrr: in isAssociativeAndCommutative()
2904 case AArch64::FMULX32: in isAssociativeAndCommutative()
2905 case AArch64::FMULX64: in isAssociativeAndCommutative()
2906 case AArch64::FMULXv2f32: in isAssociativeAndCommutative()
2907 case AArch64::FMULXv2f64: in isAssociativeAndCommutative()
2908 case AArch64::FMULXv4f32: in isAssociativeAndCommutative()
2909 case AArch64::FMULv2f32: in isAssociativeAndCommutative()
2910 case AArch64::FMULv2f64: in isAssociativeAndCommutative()
2911 case AArch64::FMULv4f32: in isAssociativeAndCommutative()
2928 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns()
2943 case AArch64::ADDWrr: in getMaddPatterns()
2946 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, in getMaddPatterns()
2947 AArch64::WZR)) { in getMaddPatterns()
2951 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr, in getMaddPatterns()
2952 AArch64::WZR)) { in getMaddPatterns()
2957 case AArch64::ADDXrr: in getMaddPatterns()
2958 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, in getMaddPatterns()
2959 AArch64::XZR)) { in getMaddPatterns()
2963 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr, in getMaddPatterns()
2964 AArch64::XZR)) { in getMaddPatterns()
2969 case AArch64::SUBWrr: in getMaddPatterns()
2970 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, in getMaddPatterns()
2971 AArch64::WZR)) { in getMaddPatterns()
2975 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDWrrr, in getMaddPatterns()
2976 AArch64::WZR)) { in getMaddPatterns()
2981 case AArch64::SUBXrr: in getMaddPatterns()
2982 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, in getMaddPatterns()
2983 AArch64::XZR)) { in getMaddPatterns()
2987 if (canCombineWithMUL(MBB, Root.getOperand(2), AArch64::MADDXrrr, in getMaddPatterns()
2988 AArch64::XZR)) { in getMaddPatterns()
2993 case AArch64::ADDWri: in getMaddPatterns()
2994 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, in getMaddPatterns()
2995 AArch64::WZR)) { in getMaddPatterns()
3000 case AArch64::ADDXri: in getMaddPatterns()
3001 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, in getMaddPatterns()
3002 AArch64::XZR)) { in getMaddPatterns()
3007 case AArch64::SUBWri: in getMaddPatterns()
3008 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDWrrr, in getMaddPatterns()
3009 AArch64::WZR)) { in getMaddPatterns()
3014 case AArch64::SUBXri: in getMaddPatterns()
3015 if (canCombineWithMUL(MBB, Root.getOperand(1), AArch64::MADDXrrr, in getMaddPatterns()
3016 AArch64::XZR)) { in getMaddPatterns()
3040 case AArch64::FADDSrr: in getFMAPatterns()
3043 if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FMULSrr)) { in getFMAPatterns()
3047 AArch64::FMULv1i32_indexed)) { in getFMAPatterns()
3051 if (canCombineWithFMUL(MBB, Root.getOperand(2), AArch64::FMULSrr)) { in getFMAPatterns()
3055 AArch64::FMULv1i32_indexed)) { in getFMAPatterns()
3060 case AArch64::FADDDrr: in getFMAPatterns()
3061 if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FMULDrr)) { in getFMAPatterns()
3065 AArch64::FMULv1i64_indexed)) { in getFMAPatterns()
3069 if (canCombineWithFMUL(MBB, Root.getOperand(2), AArch64::FMULDrr)) { in getFMAPatterns()
3073 AArch64::FMULv1i64_indexed)) { in getFMAPatterns()
3078 case AArch64::FADDv2f32: in getFMAPatterns()
3080 AArch64::FMULv2i32_indexed)) { in getFMAPatterns()
3084 AArch64::FMULv2f32)) { in getFMAPatterns()
3089 AArch64::FMULv2i32_indexed)) { in getFMAPatterns()
3093 AArch64::FMULv2f32)) { in getFMAPatterns()
3098 case AArch64::FADDv2f64: in getFMAPatterns()
3100 AArch64::FMULv2i64_indexed)) { in getFMAPatterns()
3104 AArch64::FMULv2f64)) { in getFMAPatterns()
3109 AArch64::FMULv2i64_indexed)) { in getFMAPatterns()
3113 AArch64::FMULv2f64)) { in getFMAPatterns()
3118 case AArch64::FADDv4f32: in getFMAPatterns()
3120 AArch64::FMULv4i32_indexed)) { in getFMAPatterns()
3124 AArch64::FMULv4f32)) { in getFMAPatterns()
3129 AArch64::FMULv4i32_indexed)) { in getFMAPatterns()
3133 AArch64::FMULv4f32)) { in getFMAPatterns()
3139 case AArch64::FSUBSrr: in getFMAPatterns()
3140 if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FMULSrr)) { in getFMAPatterns()
3144 if (canCombineWithFMUL(MBB, Root.getOperand(2), AArch64::FMULSrr)) { in getFMAPatterns()
3148 AArch64::FMULv1i32_indexed)) { in getFMAPatterns()
3153 case AArch64::FSUBDrr: in getFMAPatterns()
3154 if (canCombineWithFMUL(MBB, Root.getOperand(1), AArch64::FMULDrr)) { in getFMAPatterns()
3158 if (canCombineWithFMUL(MBB, Root.getOperand(2), AArch64::FMULDrr)) { in getFMAPatterns()
3162 AArch64::FMULv1i64_indexed)) { in getFMAPatterns()
3167 case AArch64::FSUBv2f32: in getFMAPatterns()
3169 AArch64::FMULv2i32_indexed)) { in getFMAPatterns()
3173 AArch64::FMULv2f32)) { in getFMAPatterns()
3178 case AArch64::FSUBv2f64: in getFMAPatterns()
3180 AArch64::FMULv2i64_indexed)) { in getFMAPatterns()
3184 AArch64::FMULv2f64)) { in getFMAPatterns()
3189 case AArch64::FSUBv4f32: in getFMAPatterns()
3191 AArch64::FMULv4i32_indexed)) { in getFMAPatterns()
3195 AArch64::FMULv4f32)) { in getFMAPatterns()
3407 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
3408 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3410 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
3411 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3422 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
3423 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3425 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
3426 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3440 OrrOpc = AArch64::ORRWri; in genAlternativeCodeSequence()
3441 OrrRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
3443 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
3444 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
3445 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3447 OrrOpc = AArch64::ORRXri; in genAlternativeCodeSequence()
3448 OrrRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
3450 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
3451 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
3452 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3484 SubOpc = AArch64::SUBWrr; in genAlternativeCodeSequence()
3485 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
3486 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
3487 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
3488 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3490 SubOpc = AArch64::SUBXrr; in genAlternativeCodeSequence()
3491 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
3492 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
3493 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
3494 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3514 Opc = AArch64::MSUBWrrr; in genAlternativeCodeSequence()
3515 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3517 Opc = AArch64::MSUBXrrr; in genAlternativeCodeSequence()
3518 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3532 OrrOpc = AArch64::ORRWri; in genAlternativeCodeSequence()
3533 OrrRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
3535 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
3536 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
3537 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3539 OrrOpc = AArch64::ORRXri; in genAlternativeCodeSequence()
3540 OrrRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
3542 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
3543 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
3544 RC = &AArch64::GPR64RegClass; in genAlternativeCodeSequence()
3573 Opc = AArch64::FMADDSrrr; in genAlternativeCodeSequence()
3574 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3576 Opc = AArch64::FMADDDrrr; in genAlternativeCodeSequence()
3577 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3588 Opc = AArch64::FMADDSrrr; in genAlternativeCodeSequence()
3589 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3591 Opc = AArch64::FMADDDrrr; in genAlternativeCodeSequence()
3592 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3598 Opc = AArch64::FMLAv1i32_indexed; in genAlternativeCodeSequence()
3599 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3604 Opc = AArch64::FMLAv1i32_indexed; in genAlternativeCodeSequence()
3605 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3611 Opc = AArch64::FMLAv1i64_indexed; in genAlternativeCodeSequence()
3612 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3617 Opc = AArch64::FMLAv1i64_indexed; in genAlternativeCodeSequence()
3618 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3625 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3627 Opc = AArch64::FMLAv2i32_indexed; in genAlternativeCodeSequence()
3631 Opc = AArch64::FMLAv2f32; in genAlternativeCodeSequence()
3638 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3640 Opc = AArch64::FMLAv2i32_indexed; in genAlternativeCodeSequence()
3644 Opc = AArch64::FMLAv2f32; in genAlternativeCodeSequence()
3652 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3654 Opc = AArch64::FMLAv2i64_indexed; in genAlternativeCodeSequence()
3658 Opc = AArch64::FMLAv2f64; in genAlternativeCodeSequence()
3665 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3667 Opc = AArch64::FMLAv2i64_indexed; in genAlternativeCodeSequence()
3671 Opc = AArch64::FMLAv2f64; in genAlternativeCodeSequence()
3679 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3681 Opc = AArch64::FMLAv4i32_indexed; in genAlternativeCodeSequence()
3685 Opc = AArch64::FMLAv4f32; in genAlternativeCodeSequence()
3693 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3695 Opc = AArch64::FMLAv4i32_indexed; in genAlternativeCodeSequence()
3699 Opc = AArch64::FMLAv4f32; in genAlternativeCodeSequence()
3712 Opc = AArch64::FNMSUBSrrr; in genAlternativeCodeSequence()
3713 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3715 Opc = AArch64::FNMSUBDrrr; in genAlternativeCodeSequence()
3716 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3728 Opc = AArch64::FMSUBSrrr; in genAlternativeCodeSequence()
3729 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3731 Opc = AArch64::FMSUBDrrr; in genAlternativeCodeSequence()
3732 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3738 Opc = AArch64::FMLSv1i32_indexed; in genAlternativeCodeSequence()
3739 RC = &AArch64::FPR32RegClass; in genAlternativeCodeSequence()
3745 Opc = AArch64::FMLSv1i64_indexed; in genAlternativeCodeSequence()
3746 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3753 RC = &AArch64::FPR64RegClass; in genAlternativeCodeSequence()
3755 Opc = AArch64::FMLSv2i32_indexed; in genAlternativeCodeSequence()
3759 Opc = AArch64::FMLSv2f32; in genAlternativeCodeSequence()
3767 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3769 Opc = AArch64::FMLSv2i64_indexed; in genAlternativeCodeSequence()
3773 Opc = AArch64::FMLSv2f64; in genAlternativeCodeSequence()
3781 RC = &AArch64::FPR128RegClass; in genAlternativeCodeSequence()
3783 Opc = AArch64::FMLSv4i32_indexed; in genAlternativeCodeSequence()
3787 Opc = AArch64::FMLSv4f32; in genAlternativeCodeSequence()
3835 case AArch64::Bcc: in optimizeCondBranch()
3837 case AArch64::CBZW: in optimizeCondBranch()
3838 case AArch64::CBZX: in optimizeCondBranch()
3841 case AArch64::CBNZW: in optimizeCondBranch()
3842 case AArch64::CBNZX: in optimizeCondBranch()
3846 case AArch64::TBZW: in optimizeCondBranch()
3847 case AArch64::TBZX: in optimizeCondBranch()
3851 case AArch64::TBNZW: in optimizeCondBranch()
3852 case AArch64::TBNZX: in optimizeCondBranch()
3889 case AArch64::ANDWri: in optimizeCondBranch()
3890 case AArch64::ANDXri: { in optimizeCondBranch()
3898 bool Is32Bit = (DefMI->getOpcode() == AArch64::ANDWri); in optimizeCondBranch()
3916 ? (IsNegativeBranch ? AArch64::TBNZW : AArch64::TBZW) in optimizeCondBranch()
3917 : (IsNegativeBranch ? AArch64::TBNZX : AArch64::TBZX); in optimizeCondBranch()
3931 NewMI->getOperand(0).setSubReg(AArch64::sub_32); in optimizeCondBranch()
3936 case AArch64::CSINCWr: in optimizeCondBranch()
3937 case AArch64::CSINCXr: { in optimizeCondBranch()
3938 if (!(DefMI->getOperand(1).getReg() == AArch64::WZR && in optimizeCondBranch()
3939 DefMI->getOperand(2).getReg() == AArch64::WZR) && in optimizeCondBranch()
3940 !(DefMI->getOperand(1).getReg() == AArch64::XZR && in optimizeCondBranch()
3941 DefMI->getOperand(2).getReg() == AArch64::XZR)) in optimizeCondBranch()
3944 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
3958 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB); in optimizeCondBranch()