Lines Matching refs:TM
141 static void initReciprocals(AArch64TargetMachine& TM, AArch64Subtarget& ST) in initReciprocals() argument
152 TM.Options.Reciprocals.setDefaults("sqrtf", UseRsqrt, ExtraStepsF); in initReciprocals()
153 TM.Options.Reciprocals.setDefaults("sqrtd", UseRsqrt, ExtraStepsD); in initReciprocals()
154 TM.Options.Reciprocals.setDefaults("vec-sqrtf", UseRsqrt, ExtraStepsF); in initReciprocals()
155 TM.Options.Reciprocals.setDefaults("vec-sqrtd", UseRsqrt, ExtraStepsD); in initReciprocals()
157 TM.Options.Reciprocals.setDefaults("divf", false, ExtraStepsF); in initReciprocals()
158 TM.Options.Reciprocals.setDefaults("divd", false, ExtraStepsD); in initReciprocals()
159 TM.Options.Reciprocals.setDefaults("vec-divf", false, ExtraStepsF); in initReciprocals()
160 TM.Options.Reciprocals.setDefaults("vec-divd", false, ExtraStepsD); in initReciprocals()
264 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM) in AArch64PassConfig() argument
265 : TargetPassConfig(TM, PM) { in AArch64PassConfig()
266 if (TM->getOptLevel() != CodeGenOpt::None) in AArch64PassConfig()
302 addPass(createAtomicExpandPass(TM)); in addIRPasses()
307 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) in addIRPasses()
314 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoopDataPrefetch) in addIRPasses()
320 if (TM->getOptLevel() != CodeGenOpt::None) in addIRPasses()
321 addPass(createInterleavedAccessPass(TM)); in addIRPasses()
323 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { in addIRPasses()
327 addPass(createSeparateConstOffsetFromGEPPass(TM, true)); in addIRPasses()
341 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant) in addPreISel()
346 if ((TM->getOptLevel() != CodeGenOpt::None && in addPreISel()
349 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && in addPreISel()
351 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize)); in addPreISel()
354 if (TM->getOptLevel() != CodeGenOpt::None) in addPreISel()
365 if (TM->getTargetTriple().isOSBinFormatELF() && in addInstSelector()
399 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) { in addPreRegAlloc()
409 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) in addPostRegAlloc()
413 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination) in addPostRegAlloc()
415 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc()) in addPostRegAlloc()
424 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt) in addPreSched2()
434 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH && in addPreEmitPass()
435 TM->getTargetTriple().isOSBinFormatMachO()) in addPreEmitPass()