Lines Matching refs:SelectionDAG
34 SelectionDAG &DAG) const;
35 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
85 SelectionDAG &DAG) const;
89 SelectionDAG &DAG) const;
90 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
91 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
94 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
97 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
103 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
111 void getOriginalFunctionArgs(SelectionDAG &DAG,
155 SelectionDAG &DAG) const override;
160 SelectionDAG &DAG) const;
162 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
166 SelectionDAG &DAG) const override;
183 SelectionDAG &DAG) const = 0;
191 const SelectionDAG &DAG,
194 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
201 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,