Lines Matching refs:DL
645 SDLoc DL(Op); in LowerOperation() local
651 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
652 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
653 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
654 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
656 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
669 SDLoc DL(Op); in LowerOperation() local
719 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
721 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
722 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
723 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
724 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
728 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
729 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
730 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
731 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
739 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
743 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
744 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
745 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
746 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
747 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
748 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
750 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
751 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
752 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
754 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
756 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
757 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
758 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
760 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
766 return DAG.getConstant(ByteOffset, DL, PtrVT); in LowerOperation()
769 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
771 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
773 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
775 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
777 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
779 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
781 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
783 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
785 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
790 return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4); in LowerOperation()
814 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
819 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1)); in LowerOperation()
867 SDLoc DL(Vector); in vectorToVerticalVector() local
875 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
876 DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout())))); in vectorToVerticalVector()
879 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
885 SDLoc DL(Op); in LowerEXTRACT_VECTOR_ELT() local
894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
900 SDLoc DL(Op); in LowerINSERT_VECTOR_ELT() local
910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
923 const DataLayout &DL = DAG.getDataLayout(); in LowerGlobalAddress() local
925 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
936 SDLoc DL(Op); in LowerTrig() local
939 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
940 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
941 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
942 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
943 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
955 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
956 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
957 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
961 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
962 DAG.getConstantFP(3.14159265359, DL, MVT::f32)); in LowerTrig()
966 SDLoc DL(Op); in LowerSHLParts() local
972 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSHLParts()
973 SDValue One = DAG.getConstant(1, DL, VT); in LowerSHLParts()
975 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSHLParts()
976 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts()
977 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
978 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
985 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
986 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
988 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
989 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
990 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
992 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
995 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
996 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
998 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
1002 SDLoc DL(Op); in LowerSRXParts() local
1008 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSRXParts()
1009 SDValue One = DAG.getConstant(1, DL, VT); in LowerSRXParts()
1013 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSRXParts()
1014 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts()
1015 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
1016 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
1023 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
1024 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
1026 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1027 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1028 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
1030 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1031 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
1033 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1034 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
1036 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
1041 SDLoc DL(Op); in LowerUADDSUBO() local
1047 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
1049 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
1052 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
1054 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
1058 SDLoc DL(Op); in LowerFPTOUINT() local
1061 DL, in LowerFPTOUINT()
1063 Op, DAG.getConstantFP(0.0f, DL, MVT::f32), in LowerFPTOUINT()
1069 const SDLoc &DL, in LowerImplicitParameter() argument
1078 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
1079 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
1109 SDLoc DL(Op); in LowerSELECT_CC() local
1121 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
1161 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1202 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
1203 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
1218 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1222 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1230 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); in LowerSELECT_CC()
1231 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); in LowerSELECT_CC()
1233 HWTrue = DAG.getConstant(-1, DL, CompareVT); in LowerSELECT_CC()
1234 HWFalse = DAG.getConstant(0, DL, CompareVT); in LowerSELECT_CC()
1242 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1244 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1272 SDLoc DL(Ptr); in stackPtrToRegIndex() local
1273 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1274 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1308 SDLoc DL(Store); in lowerPrivateTruncStore() local
1321 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr, in lowerPrivateTruncStore()
1322 DAG.getConstant(2, DL, MVT::i32)); in lowerPrivateTruncStore()
1323 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32, in lowerPrivateTruncStore()
1325 DAG.getTargetConstant(0, DL, MVT::i32)); in lowerPrivateTruncStore()
1327 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr, in lowerPrivateTruncStore()
1328 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1330 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1331 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1333 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1336 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1338 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1341 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1342 DAG.getConstant(Mask, DL, MVT::i32), in lowerPrivateTruncStore()
1344 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask, in lowerPrivateTruncStore()
1345 DAG.getConstant(0xffffffff, DL, MVT::i32)); in lowerPrivateTruncStore()
1346 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1348 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1349 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in lowerPrivateTruncStore()
1351 DAG.getTargetConstant(0, DL, MVT::i32)); in lowerPrivateTruncStore()
1368 SDLoc DL(Op); in LowerSTORE() local
1379 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1382 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1384 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, in LowerSTORE()
1385 DAG.getConstant(2, DL, MVT::i32)); in LowerSTORE()
1386 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr, in LowerSTORE()
1387 DAG.getConstant(0x00000003, DL, VT)); in LowerSTORE()
1388 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1389 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1390 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1391 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); in LowerSTORE()
1392 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift); in LowerSTORE()
1397 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1398 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1401 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1403 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL, in LowerSTORE()
1409 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(), in LowerSTORE()
1410 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
1411 Ptr, DAG.getConstant(2, DL, MVT::i32))); in LowerSTORE()
1416 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1447 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerSTORE()
1448 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerSTORE()
1449 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, in LowerSTORE()
1450 Value, DAG.getConstant(i, DL, MVT::i32)); in LowerSTORE()
1452 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in LowerSTORE()
1454 DAG.getTargetConstant(Channel, DL, MVT::i32)); in LowerSTORE()
1456 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); in LowerSTORE()
1459 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); in LowerSTORE()
1461 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr, in LowerSTORE()
1462 DAG.getTargetConstant(0, DL, MVT::i32)); // Channel in LowerSTORE()
1511 SDLoc DL(Op); in lowerPrivateExtLoad() local
1520 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), in lowerPrivateExtLoad()
1521 DAG.getConstant(2, DL, MVT::i32)); in lowerPrivateExtLoad()
1523 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(), in lowerPrivateExtLoad()
1526 DAG.getTargetConstant(0, DL, MVT::i32), in lowerPrivateExtLoad()
1530 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1532 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1535 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1536 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1539 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt); in lowerPrivateExtLoad()
1549 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode), in lowerPrivateExtLoad()
1553 return DAG.getMergeValues(Ops, DL); in lowerPrivateExtLoad()
1558 DAG.getZeroExtendInReg(Ret, DL, MemEltVT), in lowerPrivateExtLoad()
1562 return DAG.getMergeValues(Ops, DL); in lowerPrivateExtLoad()
1576 SDLoc DL(Op); in LowerLOAD() local
1586 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1604 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in LowerLOAD()
1605 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in LowerLOAD()
1606 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in LowerLOAD()
1614 Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in LowerLOAD()
1617 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1618 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1619 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1621 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1626 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1627 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1634 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1649 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
1655 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1659 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1685 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerLOAD()
1686 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerLOAD()
1687 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT, in LowerLOAD()
1689 DAG.getTargetConstant(Channel, DL, MVT::i32), in LowerLOAD()
1693 LoweredLoad = DAG.getBuildVector(TargetVT, DL, makeArrayRef(Loads, NumElemVT)); in LowerLOAD()
1695 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT, in LowerLOAD()
1697 DAG.getTargetConstant(0, DL, MVT::i32), // Channel in LowerLOAD()
1706 return DAG.getMergeValues(Ops, DL); in LowerLOAD()
1738 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
1764 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1797 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1798 DAG.getConstant(Offset, DL, MVT::i32), in LowerFormalArguments()
1810 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
1920 const SDLoc &DL) const { in OptimizeSwizzle()
1929 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1937 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
2130 SDLoc DL(N); in PerformDAGCombine() local
2131 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); in PerformDAGCombine()
2132 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2160 SDLoc DL(N); in PerformDAGCombine() local
2161 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); in PerformDAGCombine()
2162 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2373 SDLoc DL(Node); in PostISelFolding() local
2375 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32); in PostISelFolding()
2376 return DAG.getMachineNode(Src.getMachineOpcode(), DL, in PostISelFolding()