Lines Matching refs:R600InstrInfo
31 R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) in R600InstrInfo() function in R600InstrInfo
34 bool R600InstrInfo::isTrig(const MachineInstr &MI) const { in isTrig()
38 bool R600InstrInfo::isVector(const MachineInstr &MI) const { in isVector()
42 void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
77 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, in isLegalToSplitMBBAt()
88 bool R600InstrInfo::isMov(unsigned Opcode) const { in isMov()
102 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const { in isPlaceHolderOpcode()
110 bool R600InstrInfo::isReductionOp(unsigned Opcode) const { in isReductionOp()
114 bool R600InstrInfo::isCubeOp(unsigned Opcode) const { in isCubeOp()
125 bool R600InstrInfo::isALUInstr(unsigned Opcode) const { in isALUInstr()
131 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const { in hasInstrModifiers()
139 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const { in isLDSInstr()
147 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const { in isLDSNoRetInstr()
151 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const { in isLDSRetInstr()
155 bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const { in canBeConsideredALU()
173 bool R600InstrInfo::isTransOnly(unsigned Opcode) const { in isTransOnly()
179 bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const { in isTransOnly()
183 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const { in isVectorOnly()
187 bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const { in isVectorOnly()
191 bool R600InstrInfo::isExport(unsigned Opcode) const { in isExport()
195 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const { in usesVertexCache()
199 bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const { in usesVertexCache()
205 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const { in usesTextureCache()
209 bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const { in usesTextureCache()
216 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { in mustBeLastInClause()
226 bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const { in usesAddressRegister()
230 bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const { in definesAddressRegister()
234 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { in readsLDSSrcReg()
251 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const { in getSrcIdx()
262 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
286 R600InstrInfo::getSrcs(MachineInstr &MI) const { in getSrcs()
349 R600InstrInfo::ExtractSrcs(MachineInstr &MI, in ExtractSrcs()
383 R600InstrInfo::BankSwizzle Swz) { in Swizzle()
387 case R600InstrInfo::ALU_VEC_012_SCL_210: in Swizzle()
389 case R600InstrInfo::ALU_VEC_021_SCL_122: in Swizzle()
392 case R600InstrInfo::ALU_VEC_102_SCL_221: in Swizzle()
395 case R600InstrInfo::ALU_VEC_120_SCL_212: in Swizzle()
399 case R600InstrInfo::ALU_VEC_201: in Swizzle()
403 case R600InstrInfo::ALU_VEC_210: in Swizzle()
411 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { in getTransSwizzle()
413 case R600InstrInfo::ALU_VEC_012_SCL_210: { in getTransSwizzle()
417 case R600InstrInfo::ALU_VEC_021_SCL_122: { in getTransSwizzle()
421 case R600InstrInfo::ALU_VEC_120_SCL_212: { in getTransSwizzle()
425 case R600InstrInfo::ALU_VEC_102_SCL_221: { in getTransSwizzle()
438 unsigned R600InstrInfo::isLegalUpTo( in isLegalUpTo()
440 const std::vector<R600InstrInfo::BankSwizzle> &Swz, in isLegalUpTo()
442 R600InstrInfo::BankSwizzle TransSwz) const { in isLegalUpTo()
453 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 && in isLegalUpTo()
454 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) { in isLegalUpTo()
489 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in NextPossibleSolution()
493 while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) in NextPossibleSolution()
496 SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; in NextPossibleSolution()
501 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; in NextPossibleSolution()
507 bool R600InstrInfo::FindSwizzleForVectorSlot( in FindSwizzleForVectorSlot()
509 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, in FindSwizzleForVectorSlot()
511 R600InstrInfo::BankSwizzle TransSwz) const { in FindSwizzleForVectorSlot()
524 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, in isConstCompatible()
544 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG, in fitsReadPortLimitations()
559 ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle) in fitsReadPortLimitations()
570 static const R600InstrInfo::BankSwizzle TransSwz[] = { in fitsReadPortLimitations()
593 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts) in fitsConstReadLimitations()
618 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) in fitsConstReadLimitations()
648 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const { in CreateTargetScheduleState()
686 bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
769 unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB, in InsertBranch()
815 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { in RemoveBranch()
872 bool R600InstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated()
887 bool R600InstrInfo::isPredicable(MachineInstr &MI) const { in isPredicable()
911 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, in isProfitableToIfCvt()
919 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, in isProfitableToIfCvt()
930 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB, in isProfitableToDupForIfCvt()
938 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, in isProfitableToUnpredicate()
945 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
978 bool R600InstrInfo::DefinesPredicate(MachineInstr &MI, in DefinesPredicate()
985 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1, in SubsumesPredicate()
990 bool R600InstrInfo::PredicateInstruction(MachineInstr &MI, in PredicateInstruction()
1024 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const { in getPredicationCost()
1028 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency()
1036 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress()
1042 bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { in expandPostRAPseudo()
1108 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, in reserveIndirectRegisters()
1129 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const { in getIndirectAddrRegClass()
1133 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1140 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, in buildIndirectWrite()
1165 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1172 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, in buildIndirectRead()
1199 int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { in getIndirectIndexBegin()
1234 int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { in getIndirectIndexEnd()
1256 unsigned R600InstrInfo::getMaxAlusPerClause() const { in getMaxAlusPerClause()
1260 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB, in buildDefaultInstruction()
1339 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction( in buildSlotOfVectorInstruction()
1387 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB, in buildMovImm()
1397 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB, in buildMovInstr()
1403 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const { in getOperandIdx()
1407 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const { in getOperandIdx()
1411 void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op, in setImmOperand()
1423 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const { in hasFlagOperand()
1427 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp()
1492 void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand, in addFlag()
1513 void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand, in clearFlag()
1527 bool R600InstrInfo::isRegisterStore(const MachineInstr &MI) const { in isRegisterStore()
1531 bool R600InstrInfo::isRegisterLoad(const MachineInstr &MI) const { in isRegisterLoad()