55 SITargetLowering::SITargetLowering(const TargetMachine &TM,  in SITargetLowering()  function in SITargetLowering
258 const SISubtarget *SITargetLowering::getSubtarget() const {  in getSubtarget()
266 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
285 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,  in isShuffleMaskLegal()
292 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {  in isLegalFlatAddressingMode()
298 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {  in isLegalMUBUFAddressingMode()
333 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
429 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,  in allowsMisalignedMemoryAccesses()
477 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,  in getOptimalMemOpType()
503 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,  in isNoopAddrSpaceCast()
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {  in isMemOpUniform()
525 SITargetLowering::getPreferredVectorAction(EVT VT) const {  in getPreferredVectorAction()
532 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {  in isTypeDesirableForOp()
548 SDValue SITargetLowering::LowerParameterPtr(SelectionDAG &DAG,  in LowerParameterPtr()
563 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,  in LowerParameter()
588 SDValue SITargetLowering::LowerFormalArguments(  in LowerFormalArguments()
938 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
1029 unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,  in getRegisterByName()
1077 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,  in splitKillBlock()
1131 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(  in EmitInstrWithCustomInserter()
1164 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {  in enableAggressiveFMAFusion()
1175 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,  in getSetCCResultType()
1183 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {  in getScalarShiftAmountTy()
1202 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {  in isFMAFasterThanFMulAndFAdd()
1228 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
1278 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {  in LowerFrameIndex()
1315 bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {  in isCFIntrinsic()
1332 void SITargetLowering::createDebuggerPrologueStackObjects(  in createDebuggerPrologueStackObjects()
1360 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,  in LowerBRCOND()
1441 SDValue SITargetLowering::getSegmentAperture(unsigned AS,  in getSegmentAperture()
1472 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,  in lowerADDRSPACECAST()
1529 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {  in isOffsetFoldingLegal()
1560 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,  in LowerGlobalAddress()
1590 SDValue SITargetLowering::lowerTRAP(SDValue Op,  in lowerTRAP()
1607 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,  in copyToM0()
1623 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,  in lowerImplicitZextParam()
1651 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
1919 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,  in LowerINTRINSIC_W_CHAIN()
1942 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,  in LowerINTRINSIC_VOID()
1996 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerLOAD()
2087 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
2116 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFastFDIV()
2157 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV32()
2225 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV64()
2292 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {  in LowerFDIV()
2304 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {  in LowerSTORE()
2362 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {  in LowerTrig()
2382 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {  in LowerATOMIC_CMP_SWAP()
2413 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,  in performUCharToFloatCombine()
2484 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,  in performSHLPtrCombine()
2517 SDValue SITargetLowering::performAndCombine(SDNode *N,  in performAndCombine()
2574 SDValue SITargetLowering::performOrCombine(SDNode *N,  in performOrCombine()
2634 SDValue SITargetLowering::performClassCombine(SDNode *N,  in performClassCombine()
2652 SDValue SITargetLowering::performFCanonicalizeCombine(  in performFCanonicalizeCombine()
2766 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,  in performMinMaxCombine()
2827 SDValue SITargetLowering::performSetCCCombine(SDNode *N,  in performSetCCCombine()
2858 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
3068 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {  in analyzeImmediate()
3104 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,  in adjustWritemask()
3195 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,  in legalizeTargetIndependentNode()
3215 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,  in PostISelFolding()
3234 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,  in AdjustInstrPostInstrSelection()
3310 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,  in wrapAddr64Rsrc()
3345 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,  in buildRSRC()
3375 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
3389 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,  in getRegForInlineAsmConstraint()
3448 SITargetLowering::ConstraintType
3449 SITargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()