Lines Matching refs:TIDReg
737 unsigned TIDReg = MFI->getTIDReg(); in calculateLDSSpillAddress() local
743 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass); in calculateLDSSpillAddress()
744 if (TIDReg == AMDGPU::NoRegister) in calculateLDSSpillAddress()
745 return TIDReg; in calculateLDSSpillAddress()
779 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) in calculateLDSSpillAddress()
783 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) in calculateLDSSpillAddress()
786 .addReg(TIDReg); in calculateLDSSpillAddress()
788 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) in calculateLDSSpillAddress()
789 .addReg(TIDReg) in calculateLDSSpillAddress()
794 TIDReg) in calculateLDSSpillAddress()
799 TIDReg) in calculateLDSSpillAddress()
801 .addReg(TIDReg); in calculateLDSSpillAddress()
805 TIDReg) in calculateLDSSpillAddress()
807 .addReg(TIDReg); in calculateLDSSpillAddress()
808 MFI->setTIDReg(TIDReg); in calculateLDSSpillAddress()
815 .addReg(TIDReg); in calculateLDSSpillAddress()