Lines Matching refs:VRC
1889 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
1890 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove()
1891 VRC = &AMDGPU::VReg_64RegClass; in legalizeOpWithMove()
1893 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
1895 unsigned Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
2168 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
2169 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
2171 unsigned SubRegs = VRC->getSize() / 4; in readlaneVGPRToSGPR()
2231 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; in legalizeOperands() local
2239 VRC = OpRC; in legalizeOperands()
2248 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
2249 if (!VRC) { in legalizeOperands()
2251 VRC = RI.getEquivalentVGPRClass(SRC); in legalizeOperands()
2253 RC = VRC; in legalizeOperands()
2291 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands() local
2292 if (VRC == OpRC) in legalizeOperands()
2295 unsigned DstReg = MRI.createVirtualRegister(VRC); in legalizeOperands()