237     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
238     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
239     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
240     .addReg(AMDGPU::VGPR0, RegState::Undef);  in skipIfDead()
255           .addReg(Vcc);  in If()
258           .addReg(AMDGPU::EXEC)  in If()
259           .addReg(Reg);  in If()
266     .addReg(Reg);  in If()
279           .addReg(Src); // Saved EXEC  in Else()
286             .addReg(AMDGPU::EXEC)  in Else()
287             .addReg(Dst);  in Else()
291           .addReg(AMDGPU::EXEC)  in Else()
292           .addReg(Dst);  in Else()
299     .addReg(Dst);  in Else()
312           .addReg(AMDGPU::EXEC)  in Break()
313           .addReg(Src);  in Break()
327           .addReg(Vcc)  in IfBreak()
328           .addReg(Src);  in IfBreak()
342           .addReg(Saved)  in ElseBreak()
343           .addReg(Src);  in ElseBreak()
354           .addReg(AMDGPU::EXEC)  in Loop()
355           .addReg(Src);  in Loop()
370           .addReg(AMDGPU::EXEC)  in EndCf()
371           .addReg(Reg);  in EndCf()
421   RemainderLiveRegs.addReg(SaveReg);  in splitLoadM0BlockLiveIns()
425       RemainderLiveRegs.addReg(Val->getReg());  in splitLoadM0BlockLiveIns()
453     .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));  in emitLoadM0FromVGPRLoop()
457     .addReg(AMDGPU::VCC_LO);  in emitLoadM0FromVGPRLoop()
461     .addReg(AMDGPU::M0)  in emitLoadM0FromVGPRLoop()
462     .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));  in emitLoadM0FromVGPRLoop()
466     .addReg(AMDGPU::VCC);  in emitLoadM0FromVGPRLoop()
470       .addReg(AMDGPU::M0)  in emitLoadM0FromVGPRLoop()
479     .addReg(AMDGPU::EXEC)  in emitLoadM0FromVGPRLoop()
480     .addReg(AMDGPU::VCC);  in emitLoadM0FromVGPRLoop()
536         .addReg(Idx->getReg(), getUndefRegState(Idx->isUndef()))  in loadM0()
540         .addReg(Idx->getReg(), getUndefRegState(Idx->isUndef()));  in loadM0()
558     .addReg(AMDGPU::EXEC);  in loadM0()
583     .addReg(Save);  in loadM0()
643       .addReg(Reg, getUndefRegState(SrcVec->isUndef()));  in indirectSrc()
650     .addReg(Reg, getUndefRegState(SrcVec->isUndef()))  in indirectSrc()
651     .addReg(SrcVec->getReg(), RegState::Implicit);  in indirectSrc()
679     .addReg(Val->getReg(), getUndefRegState(Val->isUndef()))  in indirectDst()
680     .addReg(Dst, RegState::Implicit);  in indirectDst()