84   const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in canShrink()
95       case AMDGPU::V_MAC_F32_e64:  in canShrink()
97             TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))  in canShrink()
101       case AMDGPU::V_CNDMASK_B32_e64:  in canShrink()
106   const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);  in canShrink()
108       TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);  in canShrink()
115   if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))  in canShrink()
119   if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))  in canShrink()
122   return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);  in canShrink()
138   int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in foldImmediates()
185     if (Use.getReg() == AMDGPU::VCC) {  in copyFlagsToImplicitVCC()
217       if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {  in runOnMachineFunction()
233               MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));  in runOnMachineFunction()
248       if (MI.getOpcode() == AMDGPU::S_NOP &&  in runOnMachineFunction()
250           (*Next).getOpcode() == AMDGPU::S_NOP) {  in runOnMachineFunction()
273       if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||  in runOnMachineFunction()
274           MI.getOpcode() == AMDGPU::S_MUL_I32) {  in runOnMachineFunction()
290             unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?  in runOnMachineFunction()
291               AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;  in runOnMachineFunction()
300       if (MI.getOpcode() == AMDGPU::S_MOV_B32) {  in runOnMachineFunction()
304           MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));  in runOnMachineFunction()
325       int Op32 = AMDGPU::getVOPe32(MI.getOpcode());  in runOnMachineFunction()
338           MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);  in runOnMachineFunction()
341         if (DstReg != AMDGPU::VCC)  in runOnMachineFunction()
345       if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {  in runOnMachineFunction()
349             TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in runOnMachineFunction()
354           MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);  in runOnMachineFunction()
357         if (SReg != AMDGPU::VCC)  in runOnMachineFunction()
369       int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);  in runOnMachineFunction()
374         assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&  in runOnMachineFunction()
379       Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));  in runOnMachineFunction()
382           TII->getNamedOperand(MI, AMDGPU::OpName::src1);  in runOnMachineFunction()
387         TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in runOnMachineFunction()
389         int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);  in runOnMachineFunction()