852 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()  function in ARMBaseInstrInfo
899           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
900           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
910           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
911           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
946           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
947           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
948           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
967           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
968           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
969           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
970                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
981         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
982         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
983         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
984         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
985         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);  in storeRegToStackSlot()
986         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);  in storeRegToStackSlot()
987         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);  in storeRegToStackSlot()
988               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);  in storeRegToStackSlot()
1081         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1082         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1091         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1092         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1125         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1126         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1127         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1145         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1146         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1147         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1148         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1161       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1162       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1163       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1164       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1165       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1166       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1167       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1168       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()