Lines Matching refs:MIB
685 MachineInstrBuilder MIB = in copyFromCPSR() local
691 MIB.addImm(0x800); in copyFromCPSR()
693 AddDefaultPred(MIB); in copyFromCPSR()
695 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
706 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR() local
709 MIB.addImm(0x800); in copyToCPSR()
711 MIB.addImm(8); in copyToCPSR()
713 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyToCPSR()
715 AddDefaultPred(MIB); in copyToCPSR()
717 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
749 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local
750 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
752 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
753 AddDefaultPred(MIB); in copyPhysReg()
852 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() argument
856 return MIB.addReg(Reg, State); in AddDReg()
859 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg()
860 return MIB.addReg(Reg, State, SubIdx); in AddDReg()
898 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot() local
899 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
900 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
901 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); in storeRegToStackSlot()
903 AddDefaultPred(MIB); in storeRegToStackSlot()
907 MachineInstrBuilder MIB = in storeRegToStackSlot() local
910 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
911 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
942 MachineInstrBuilder MIB = in storeRegToStackSlot() local
946 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
947 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
948 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
963 MachineInstrBuilder MIB = in storeRegToStackSlot() local
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
970 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
977 MachineInstrBuilder MIB = in storeRegToStackSlot() local
981 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
982 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
983 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
984 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
985 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
986 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
987 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
988 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1077 MachineInstrBuilder MIB; in loadRegFromStackSlot() local
1080 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1081 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1082 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1083 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
1085 AddDefaultPred(MIB); in loadRegFromStackSlot()
1089 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1091 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1092 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1096 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1121 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1125 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1126 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1127 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1129 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1141 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1145 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1146 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1147 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1148 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1150 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1157 MachineInstrBuilder MIB = in loadRegFromStackSlot() local
1161 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1162 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1163 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1164 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1165 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1166 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1167 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1168 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1170 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1329 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in expandPostRAPseudo() local
1341 AddDefaultPred(MIB); in expandPostRAPseudo()
1348 MIB.addReg(SrcRegS, RegState::Implicit); in expandPostRAPseudo()
1424 MachineInstrBuilder MIB = in reMaterialize() local
1428 MIB->setMemRefs(Orig.memoperands_begin(), Orig.memoperands_end()); in reMaterialize()
2136 MachineInstrBuilder MIB(MF, &*MI); in tryFoldSPUpdateIntoPushPop() local
2138 MIB.addOperand(RegList[i]); in tryFoldSPUpdateIntoPushPop()
4127 MachineInstrBuilder MIB; in expandLoadStackGuardBase() local
4133 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4134 MIB.addReg(Reg, RegState::Kill).addImm(0); in expandLoadStackGuardBase()
4138 MIB.addMemOperand(MMO); in expandLoadStackGuardBase()
4139 AddDefaultPred(MIB); in expandLoadStackGuardBase()
4142 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4143 MIB.addReg(Reg, RegState::Kill).addImm(0); in expandLoadStackGuardBase()
4144 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuardBase()
4145 AddDefaultPred(MIB); in expandLoadStackGuardBase()
4278 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in setExecutionDomain() local
4304 MIB.addReg(DstReg, RegState::Define).addReg(SrcReg).addReg(SrcReg)); in setExecutionDomain()
4324 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) in setExecutionDomain()
4330 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4353 MIB.addReg(DReg, RegState::Define) in setExecutionDomain()
4357 AddDefaultPred(MIB); in setExecutionDomain()
4361 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
4363 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4389 MIB.addReg(DDst, RegState::Define) in setExecutionDomain()
4392 AddDefaultPred(MIB); in setExecutionDomain()
4396 MIB.addReg(DstReg, RegState::Implicit | RegState::Define); in setExecutionDomain()
4397 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4399 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()
4437 MIB.addReg(DDst, RegState::Define); in setExecutionDomain()
4443 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4447 MIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
4449 MIB.addImm(1); in setExecutionDomain()
4450 AddDefaultPred(MIB); in setExecutionDomain()
4453 MIB.addReg(SrcReg, RegState::Implicit); in setExecutionDomain()
4457 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); in setExecutionDomain()
4459 MIB.addReg(ImplicitSReg, RegState::Implicit); in setExecutionDomain()