Lines Matching refs:MIB
401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
443 MIB.addOperand(MO); in ExpandVLD()
446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
447 TransferImpOps(MI, MIB, MIB); in ExpandVLD()
450 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVLD()
466 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST() local
470 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
473 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
474 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
477 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
484 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
486 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
488 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
490 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
493 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
494 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
497 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandVST()
499 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
500 TransferImpOps(MI, MIB, MIB); in ExpandVST()
503 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVST()
520 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp() local
542 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
544 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
546 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
548 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
552 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
555 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
556 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
559 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
569 MIB.addReg(D0, SrcFlags); in ExpandLaneOp()
571 MIB.addReg(D1, SrcFlags); in ExpandLaneOp()
573 MIB.addReg(D2, SrcFlags); in ExpandLaneOp()
575 MIB.addReg(D3, SrcFlags); in ExpandLaneOp()
578 MIB.addImm(Lane); in ExpandLaneOp()
582 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
583 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandLaneOp()
587 MIB.addOperand(MO); in ExpandLaneOp()
590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
591 TransferImpOps(MI, MIB, MIB); in ExpandLaneOp()
593 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandLaneOp()
604 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL() local
608 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
610 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
616 MIB.addReg(D0); in ExpandVTBL()
619 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
622 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
623 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVTBL()
626 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); in ExpandVTBL()
627 TransferImpOps(MI, MIB, MIB); in ExpandVTBL()
792 MachineInstrBuilder MIB = in ExpandCMP_SWAP() local
796 MIB.addImm(0); in ExpandCMP_SWAP()
797 AddDefaultPred(MIB); in ExpandCMP_SWAP()
809 MachineInstrBuilder MIB; in ExpandCMP_SWAP() local
810 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg()); in ExpandCMP_SWAP()
811 MIB.addReg(Addr.getReg()); in ExpandCMP_SWAP()
813 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset. in ExpandCMP_SWAP()
814 AddDefaultPred(MIB); in ExpandCMP_SWAP()
837 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg); in ExpandCMP_SWAP()
838 MIB.addOperand(New); in ExpandCMP_SWAP()
839 MIB.addOperand(Addr); in ExpandCMP_SWAP()
841 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset. in ExpandCMP_SWAP()
842 AddDefaultPred(MIB); in ExpandCMP_SWAP()
869 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, in addExclusiveRegPair() argument
875 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
876 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
878 MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
924 MachineInstrBuilder MIB; in ExpandCMP_SWAP_64() local
925 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD)); in ExpandCMP_SWAP_64()
926 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI); in ExpandCMP_SWAP_64()
927 MIB.addReg(Addr.getReg()); in ExpandCMP_SWAP_64()
928 AddDefaultPred(MIB); in ExpandCMP_SWAP_64()
936 MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr)) in ExpandCMP_SWAP_64()
940 AddDefaultPred(MIB); in ExpandCMP_SWAP_64()
941 MIB.addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
960 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg); in ExpandCMP_SWAP_64()
961 addExclusiveRegPair(MIB, New, 0, IsThumb, TRI); in ExpandCMP_SWAP_64()
962 MIB.addOperand(Addr); in ExpandCMP_SWAP_64()
963 AddDefaultPred(MIB); in ExpandCMP_SWAP_64()
1017 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in ExpandMI() local
1019 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in ExpandMI()
1023 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in ExpandMI()
1029 MIB.addImm(ARMCC::AL).addReg(0); in ExpandMI()
1216 MachineInstrBuilder MIB = in ExpandMI() local
1222 TransferImpOps(MI, MIB, MIB); in ExpandMI()
1228 MachineInstrBuilder MIB; in ExpandMI() local
1230 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandMI()
1235 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandMI()
1239 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
1240 TransferImpOps(MI, MIB, MIB); in ExpandMI()
1297 MachineInstrBuilder MIB = in ExpandMI() local
1301 MIB.addImm(0); in ExpandMI()
1302 AddDefaultPred(MIB); in ExpandMI()
1305 MachineInstrBuilder MIB = in ExpandMI() local
1312 AddDefaultPred(MIB); in ExpandMI()
1368 MachineInstrBuilder MIB = in ExpandMI() local
1375 TransferImpOps(MI, MIB, MIB); in ExpandMI()
1381 MachineInstrBuilder MIB = in ExpandMI() local
1390 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1393 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1394 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1399 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
1403 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
1404 TransferImpOps(MI, MIB, MIB); in ExpandMI()
1405 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
1412 MachineInstrBuilder MIB = in ExpandMI() local
1421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1424 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandMI()
1430 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) in ExpandMI()
1434 MIB->addRegisterKilled(SrcReg, TRI, true); in ExpandMI()
1436 TransferImpOps(MI, MIB, MIB); in ExpandMI()
1437 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()