Lines Matching refs:NextReg
1128 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1139 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1141 NextReg += 4; in emitAlignedDPRCS2Spills()
1147 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg) in emitAlignedDPRCS2Spills()
1157 NextReg += 4; in emitAlignedDPRCS2Spills()
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1168 NextReg += 2; in emitAlignedDPRCS2Spills()
1174 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()
1177 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1178 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2)); in emitAlignedDPRCS2Spills()
1247 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores() local
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1253 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1257 NextReg += 4; in emitAlignedDPRCS2Restores()
1263 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Restores()
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1269 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1272 NextReg += 4; in emitAlignedDPRCS2Restores()
1278 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1282 NextReg += 2; in emitAlignedDPRCS2Restores()
1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1289 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg))); in emitAlignedDPRCS2Restores()