88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,  in addTypeForNEON()
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {  in addDRTypeForNEON()
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {  in addQRTypeForNEON()
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,  in ARMTargetLowering()  function in ARMTargetLowering
1062 bool ARMTargetLowering::useSoftFloat() const {  in useSoftFloat()
1077 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,  in findRepresentativeClass()
1114 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
1251 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,  in getSetCCResultType()
1260 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {  in getRegClassFor()
1276 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,  in shouldAlignPointerArgs()
1289 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,  in createFastISel()
1294 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {  in getSchedulingPreference()
1384 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,  in getEffectiveCallingConv()
1422 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,  in CCAssignFnForNode()
1445 SDValue ARMTargetLowering::LowerCallResult(  in LowerCallResult()
1529 SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,  in LowerMemOpCallTo()
1544 void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,  in PassF64ArgInRegs()
1575 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,  in LowerCall()
1984 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,  in HandleByVal()
2086 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,  in IsEligibleForTailCallOptimization()
2213 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,  in CanLowerReturn()
2257 ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,  in LowerReturn()
2381 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {  in isUsedByReturnOnly()
2456 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {  in mayBeEmittedAsTailCall()
2507 unsigned ARMTargetLowering::getJumpTableEncoding() const {  in getJumpTableEncoding()
2511 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,  in LowerBlockAddress()
2567 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,  in LowerGlobalTLSAddressDarwin()
2609 ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,  in LowerGlobalTLSAddressWindows()
2669 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,  in LowerToTLSGeneralDynamicModel()
2711 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,  in LowerToTLSExecModels()
2766 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {  in LowerGlobalTLSAddress()
2792 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,  in LowerGlobalAddressELF()
2845 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,  in LowerGlobalAddressDarwin()
2869 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,  in LowerGlobalAddressWindows()
2897 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {  in LowerEH_SJLJ_SETJMP()
2906 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {  in LowerEH_SJLJ_LONGJMP()
2912 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,  in LowerEH_SJLJ_SETUP_DISPATCH()
2920 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,  in LowerINTRINSIC_WO_CHAIN()
3073 SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,  in GetF64FormalArgument()
3119 int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,  in StoreByValRegs()
3174 void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,  in VarArgStyleRegisters()
3193 SDValue ARMTargetLowering::LowerFormalArguments(  in LowerFormalArguments()
3421 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,  in getARMCmp()
3479 SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,  in getVFPCmp()
3493 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {  in duplicateCmp()
3512 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,  in getARMXALUOOp()
3556 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {  in LowerXALUO()
3579 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT()
3697 SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,  in getCMOV()
3849 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerSELECT_CC()
4010 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {  in OptimizeVFPBrcond()
4060 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_CC()
4114 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {  in LowerBR_JT()
4171 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_TO_INT()
4223 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {  in LowerINT_TO_FP()
4242 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {  in LowerFCOPYSIGN()
4324 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{  in LowerRETURNADDR()
4348 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {  in LowerFRAMEADDR()
4369 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,  in getRegisterByName()
4517 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,  in LowerShiftRightParts()
4553 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,  in LowerShiftLeftParts()
4585 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,  in LowerFLT_ROUNDS_()
5173 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,  in LowerConstantFP()
5647 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,  in LowerBUILD_VECTOR()
5856 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,  in ReconstructShuffle()
6062 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,  in isShuffleMaskLegal()
6912 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {  in LowerFSINCOS()
6988 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,  in LowerWindowsDIVLibCall()
7007   ARMTargetLowering::ArgListTy Args;  in LowerWindowsDIVLibCall()
7025 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,  in LowerDIV_Windows()
7037 void ARMTargetLowering::ExpandDIV_Windows(  in ExpandDIV_Windows()
7140 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {  in LowerOperation()
7232 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
7282 void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,  in SetupEntryBlockForSjLj()
7398 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,  in EmitSjLjDispatchBlock()
7896 ARMTargetLowering::EmitStructByval(MachineInstr &MI,  in EmitStructByval()
8130 ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,  in EmitLowered__chkstk()
8198 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,  in EmitLowered__dbzchk()
8226 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,  in EmitInstrWithCustomInserter()
8513 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,  in AdjustInstrPostInstrSelection()
10813 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {  in PerformCMOVToBFICombine()
10906 ARMTargetLowering::PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const {  in PerformBRCONDCombine()
10946 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {  in PerformCMOVCombine()
11030 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
11095 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,  in isDesirableToTransformToIntegerOp()
11100 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,  in allowsMisalignedMemoryAccesses()
11142 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,  in getOptimalMemOpType()
11175 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
11196 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {  in isVectorLoadExtDesirable()
11218 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {  in allowTruncateForTailCall()
11330 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,  in isLegalT2ScaledAddressingMode()
11365 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,  in isLegalAddressingMode()
11429 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {  in isLegalICmpImmediate()
11443 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {  in isLegalAddImmediate()
11542 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,  in getPreIndexedAddressParts()
11580 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,  in getPostIndexedAddressParts()
11628 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,  in computeKnownBitsForTargetNode()
11678 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {  in ExpandInlineAsm()
11709 const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const {  in LowerXConstraint()
11731 ARMTargetLowering::ConstraintType
11732 ARMTargetLowering::getConstraintType(StringRef Constraint) const {  in getConstraintType()
11760 ARMTargetLowering::getSingleConstraintMatchWeight(  in getSingleConstraintMatchWeight()
11791 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(  in getRegForInlineAsmConstraint()
11842 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,  in LowerAsmOperandForConstraint()
12046 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {  in LowerDivRem()
12081 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {  in LowerREM()
12121 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {  in LowerDYNAMIC_STACKALLOC()
12146 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_EXTEND()
12158 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFP_ROUND()
12172 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {  in isOffsetFoldingLegal()
12189 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {  in isFPImmLegal()
12202 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,  in getTgtMemIntrinsic()
12315 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,  in shouldConvertConstantLoadToIntImm()
12325 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,  in makeDMB()
12355 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,  in emitLeadingFence()
12380 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,  in emitTrailingFence()
12402 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {  in shouldExpandAtomicStoreInIR()
12415 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {  in shouldExpandAtomicLoadInIR()
12424 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {  in shouldExpandAtomicRMWInIR()
12431 bool ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(  in shouldExpandAtomicCmpXchgInIR()
12441 bool ARMTargetLowering::shouldInsertFencesForAtomic(  in shouldInsertFencesForAtomic()
12447 bool ARMTargetLowering::useLoadStackGuardNode() const {  in useLoadStackGuardNode()
12451 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,  in canCombineStoreAndExtract()
12480 bool ARMTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
12484 bool ARMTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
12488 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,  in emitLoadLinked()
12524 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(  in emitAtomicCmpXchgNoStoreLLBalance()
12532 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,  in emitStoreConditional()
12576 bool ARMTargetLowering::lowerInterleavedLoad(  in lowerInterleavedLoad()
12664 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,  in lowerInterleavedStore()
12790 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(  in functionArgumentNeedsConsecutiveRegisters()
12805 unsigned ARMTargetLowering::getExceptionPointerRegister(  in getExceptionPointerRegister()
12812 unsigned ARMTargetLowering::getExceptionSelectorRegister(  in getExceptionSelectorRegister()
12819 void ARMTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {  in initializeSplitCSR()
12825 void ARMTargetLowering::insertCopiesSplitCSR(  in insertCopiesSplitCSR()