Lines Matching refs:VReg1
7516 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7517 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) in EmitSjLjDispatchBlock()
7520 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
7524 .addReg(VReg1) in EmitSjLjDispatchBlock()
7576 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7578 .addReg(VReg1, RegState::Define) in EmitSjLjDispatchBlock()
7582 .addReg(VReg1)); in EmitSjLjDispatchBlock()
7639 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7640 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) in EmitSjLjDispatchBlock()
7643 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
7647 .addReg(VReg1) in EmitSjLjDispatchBlock()
7665 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7667 .addReg(VReg1, RegState::Define) in EmitSjLjDispatchBlock()
7672 .addReg(VReg1, RegState::Kill)); in EmitSjLjDispatchBlock()