Lines Matching refs:N2RegVShRFrm

3155            (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3167            (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3175            (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3876 //   with f of either N2RegVShLFrm or N2RegVShRFrm
3919   def v8i8  : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3923   def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3927   def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3931   def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3936   def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3940   def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3944   def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3948   def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3993 //   with f of either N2RegVShLFrm or N2RegVShRFrm
4035                         N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
4039                         N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
4043                         N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
4047                         N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
4052                         N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
4056                         N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
4060                         N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
4064                         N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;