Lines Matching refs:Sched
359 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
372 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
392 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
403 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
424 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
436 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
452 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
461 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
471 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
476 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
489 Requires<[IsThumb]>, Sched<[WriteBrL]> {
502 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
517 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
527 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
538 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
545 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
558 Sched<[WriteBrTbl]>;
564 Sched<[WriteBrTbl]> {
576 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
592 Requires<[IsThumb]>, Sched<[WriteBr]>;
602 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
612 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
622 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
912 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
920 Sched<[WriteALU]> {
930 Sched<[WriteALU]>;
938 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
943 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
958 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
966 Sched<[WriteALU]> {
976 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
984 Sched<[WriteALU]>;
1000 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1009 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
1022 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
1026 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
1043 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1051 Sched<[WriteALU]> {
1061 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1069 Sched<[WriteALU]> {
1079 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1086 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1104 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1114 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1145 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1153 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1161 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1168 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1175 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1183 Sched<[WriteALU]>;
1190 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1199 Sched<[WriteALU]>;
1207 Sched<[WriteALU]> {
1217 Sched<[WriteALU]>;
1225 Sched<[WriteALU]>;
1234 Sched<[WriteALU]>;
1243 Sched<[WriteALU]>;
1251 Sched<[WriteALU]>;
1269 Sched<[WriteALU]>;
1277 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1292 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1302 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1307 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1319 Sched<[WriteBr]>;
1533 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1539 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;