Lines Matching refs:ARM_AM
204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
525 ARM_AM::ShiftOpc ShiftTy;
535 ARM_AM::ShiftOpc ShiftTy;
542 ARM_AM::ShiftOpc ShiftTy;
751 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); in isFPImm()
1022 return (ARM_AM::getSOImmVal(Value) != -1 || in isAdrLabel()
1023 ARM_AM::getSOImmVal(-Value) != -1); in isAdrLabel()
1030 return ARM_AM::getT2SOImmVal(Value) != -1; in isT2SOImm()
1037 return ARM_AM::getT2SOImmVal(Value) == -1 && in isT2SOImmNot()
1038 ARM_AM::getT2SOImmVal(~Value) != -1; in isT2SOImmNot()
1046 return ARM_AM::getT2SOImmVal(Value) == -1 && in isT2SOImmNeg()
1047 ARM_AM::getT2SOImmVal(-Value) != -1; in isT2SOImmNeg()
1074 return ARM_AM::getSOImmVal(~Value) != -1; in isModImmNot()
1081 return ARM_AM::getSOImmVal(Value) == -1 && in isModImmNeg()
1082 ARM_AM::getSOImmVal(-Value) != -1; in isModImmNeg()
1088 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1195 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1209 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1248 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1269 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1279 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1634 return ARM_AM::isNEONi16splat(Value); in isNEONi16splat()
1644 return ARM_AM::isNEONi16splat(~Value & 0xffff); in isNEONi16splatNot()
1656 return ARM_AM::isNEONi32splat(Value); in isNEONi32splat()
1666 return ARM_AM::isNEONi32splat(~Value); in isNEONi32splatNot()
1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1819 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
1863 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands()
1870 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands()
1905 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); in addFPImmOperands()
2122 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode2Operands()
2126 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2130 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, in addAddrMode2Operands()
2143 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM2OffsetImmOperands()
2147 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2166 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode3Operands()
2170 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAddrMode3Operands()
2174 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); in addAddrMode3Operands()
2185 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
2194 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM3OffsetOperands()
2198 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAM3OffsetOperands()
2216 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5Operands()
2220 Val = ARM_AM::getAM5Opc(AddSub, Val); in addAddrMode5Operands()
2238 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5FP16Operands()
2242 Val = ARM_AM::getAM5FP16Opc(AddSub, Val); in addAddrMode5FP16Operands()
2339 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, in addMemRegOffsetOperands()
2421 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
2422 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, in addPostIdxRegShiftedOperands()
2481 Value = ARM_AM::encodeNEONi16splat(Value); in addNEONi16splatOperands()
2490 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); in addNEONi16splatNotOperands()
2499 Value = ARM_AM::encodeNEONi32splat(Value); in addNEONi32splatOperands()
2508 Value = ARM_AM::encodeNEONi32splat(~Value); in addNEONi32splatNotOperands()
2649 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
2663 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
2804 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
2929 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
2930 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " in print()
2953 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) in print()
2959 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) in print()
3098 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
3099 .Case("asl", ARM_AM::lsl) in tryParseShiftRegister()
3100 .Case("lsl", ARM_AM::lsl) in tryParseShiftRegister()
3101 .Case("lsr", ARM_AM::lsr) in tryParseShiftRegister()
3102 .Case("asr", ARM_AM::asr) in tryParseShiftRegister()
3103 .Case("ror", ARM_AM::ror) in tryParseShiftRegister()
3104 .Case("rrx", ARM_AM::rrx) in tryParseShiftRegister()
3105 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
3107 if (ShiftTy == ARM_AM::no_shift) in tryParseShiftRegister()
3124 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
3151 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
3152 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
3159 ShiftTy = ARM_AM::lsl; in tryParseShiftRegister()
3175 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4492 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm()
4666 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg()
4748 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
4857 ARM_AM::no_shift, 0, 0, false, in parseMemory()
4914 ARM_AM::no_shift, 0, Align, in parseMemory()
4963 ARM_AM::no_shift, 0, 0, in parseMemory()
4992 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; in parseMemory()
5024 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, in parseMemRegOffsetShift()
5034 St = ARM_AM::lsl; in parseMemRegOffsetShift()
5036 St = ARM_AM::lsr; in parseMemRegOffsetShift()
5038 St = ARM_AM::asr; in parseMemRegOffsetShift()
5040 St = ARM_AM::ror; in parseMemRegOffsetShift()
5042 St = ARM_AM::rrx; in parseMemRegOffsetShift()
5049 if (St != ARM_AM::rrx) { in parseMemRegOffsetShift()
5069 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || in parseMemRegOffsetShift()
5070 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) in parseMemRegOffsetShift()
5074 St = ARM_AM::lsl; in parseMemRegOffsetShift()
5153 float RealVal = ARM_AM::getFPImmFloat(Val); in parseFPImm()
6876 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); in processInstruction()
6948 if (ARM_AM::getSOImmVal(Value) != -1) { in processInstruction()
6949 Value = ARM_AM::getSOImmVal(Value); in processInstruction()
6952 else if (ARM_AM::getSOImmVal(~Value) != -1) { in processInstruction()
6953 Value = ARM_AM::getSOImmVal(~Value); in processInstruction()
6967 ARM_AM::getT2SOImmVal(Value) != -1) in processInstruction()
6970 ARM_AM::getT2SOImmVal(~Value) != -1) { in processInstruction()
8118 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { in processInstruction()
8120 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; in processInstruction()
8121 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; in processInstruction()
8122 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; in processInstruction()
8123 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; in processInstruction()
8152 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { in processInstruction()
8154 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; in processInstruction()
8155 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; in processInstruction()
8156 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; in processInstruction()
8157 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; in processInstruction()
8158 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; in processInstruction()
8160 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); in processInstruction()
8183 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
8186 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; in processInstruction()
8187 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; in processInstruction()
8188 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; in processInstruction()
8189 case ARM::RORr: ShiftTy = ARM_AM::ror; break; in processInstruction()
8191 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); in processInstruction()
8208 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
8211 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; in processInstruction()
8212 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; in processInstruction()
8213 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; in processInstruction()
8214 case ARM::RORi: ShiftTy = ARM_AM::ror; break; in processInstruction()
8220 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) in processInstruction()
8222 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); in processInstruction()
8236 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); in processInstruction()
8318 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8327 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) in processInstruction()
8584 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); in processInstruction()
8586 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) in processInstruction()
8588 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { in processInstruction()
8609 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); in processInstruction()
8610 if (SOpc == ARM_AM::rrx) return false; in processInstruction()
8622 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && in processInstruction()
8623 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { in processInstruction()