525     ARM_AM::ShiftOpc ShiftTy;  member
535     ARM_AM::ShiftOpc ShiftTy;  member
542     ARM_AM::ShiftOpc ShiftTy;  member
1088     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;  in isPostIdxReg()
1209       return PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isAM3Offset()
1808       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
1819       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
2423                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
2653     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
2666     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
2822   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
2827     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
2929     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
2930       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
2953        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)  in print()
2959        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)  in print()
3098   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)  in tryParseShiftRegister()  local
3107   if (ShiftTy == ARM_AM::no_shift)  in tryParseShiftRegister()
3124   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
3151           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
3152           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
3159         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
3175   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
3176     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,  in tryParseShiftRegister()
3180     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
4666   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
4670     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
4677   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,  in parsePostIdxReg()
8183     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
8186     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
8187     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
8188     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
8189     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
8191     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
8208     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
8211     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
8212     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
8213     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
8214     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
8220     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
8222     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()