367     assert(RR.Sub == 0);  in getSubregMask()
373     if (RR.Sub == 0) {  in getSubregMask()
378     assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);  in getSubregMask()
380     Begin = (RR.Sub == Hexagon::subreg_loreg ? 0 : 32);  in getSubregMask()
854   if (RR.Sub == 0)  in getFinalVRegClass()
857   auto VerifySR = [] (unsigned Sub) -> void {  in getFinalVRegClass()  argument
858     assert(Sub == Hexagon::subreg_hireg || Sub == Hexagon::subreg_loreg);  in getFinalVRegClass()
863       VerifySR(RR.Sub);  in getFinalVRegClass()
866       VerifySR(RR.Sub);  in getFinalVRegClass()
869       VerifySR(RR.Sub);  in getFinalVRegClass()
1296           .addReg(RS.Reg, 0, RS.Sub);  in processBlock()
1297       HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);  in processBlock()
1509       Out.Sub = 0;  in findMatch()
1521       Out.Sub = Hexagon::subreg_loreg;  in findMatch()
1523       Out.Sub = Hexagon::subreg_hireg;  in findMatch()
1558         .addReg(MR.Reg, 0, MR.Sub);  in processBlock()
1597       if (RS.Sub != 0)  in propagateRegCopy()
1598         Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI);  in propagateRegCopy()
1607                                          SL.Reg, SL.Sub, MRI);  in propagateRegCopy()
1609                                           SH.Reg, SH.Sub, MRI);  in propagateRegCopy()
1616                                        RL.Reg, RL.Sub, MRI);  in propagateRegCopy()
1618                                         RH.Reg, RH.Sub, MRI);  in propagateRegCopy()
1624       unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::subreg_loreg  in propagateRegCopy()  local
1627       Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI);  in propagateRegCopy()
1746   unsigned Sub = 0;  in matchHalf()  local
1749       Sub = Hexagon::subreg_loreg;  in matchHalf()
1753       Sub = Hexagon::subreg_loreg;  in matchHalf()
1757       Sub = Hexagon::subreg_hireg;  in matchHalf()
1761       Sub = Hexagon::subreg_hireg;  in matchHalf()
1769   RH.Sub = Sub;  in matchHalf()
1773     RH.Sub = 0;  in matchHalf()
1792   if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low)  in matchPackhl()
1794   if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low)  in matchPackhl()
1831   ValOp.setSubReg(H.Sub);  in genStoreUpperHalf()
1924       .addReg(Rs.Reg, 0, Rs.Sub)  in genPackhl()
1925       .addReg(Rt.Reg, 0, Rt.Sub);  in genPackhl()
1926   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);  in genPackhl()
1953         .addReg(L.Reg, 0, L.Sub);  in genExtractHalf()
1957         .addReg(L.Reg, 0, L.Sub)  in genExtractHalf()
1962   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);  in genExtractHalf()
1977   if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low)  in genCombineHalf()
1991       .addReg(H.Reg, 0, H.Sub)  in genCombineHalf()
1992       .addReg(L.Reg, 0, L.Sub);  in genCombineHalf()
1993   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);  in genCombineHalf()
2047                   .addReg(RS.Reg, 0, RS.Sub);  in genExtractLow()
2052     HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);  in genExtractLow()
2093       RR.Sub = Hexagon::subreg_loreg;  in simplifyTstbit()
2096         RR.Sub = Hexagon::subreg_hireg;  in simplifyTstbit()
2104           .addReg(RR.Reg, 0, RR.Sub)  in simplifyTstbit()
2554              << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()  in processLoop()
2555              << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"  in processLoop()
2675              << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)  in processLoop()
2676              << "  out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";  in processLoop()