1472   bool Is128B = HST.useHVXDblOps();  in expandStoreVecPred()  local
1473   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandStoreVecPred()
1486   unsigned VandOpc = !Is128B ? Hexagon::V6_vandqrt : Hexagon::V6_vandqrt_128B;  in expandStoreVecPred()
1512   bool Is128B = HST.useHVXDblOps();  in expandLoadVecPred()  local
1513   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandLoadVecPred()
1528   unsigned VandOpc = !Is128B ? Hexagon::V6_vandvrt : Hexagon::V6_vandvrt_128B;  in expandLoadVecPred()
1557   bool Is128B = HST.useHVXDblOps();  in expandStoreVec2()  local
1558   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandStoreVec2()
1567     StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai  : Hexagon::V6_vS32b_ai_128B;  in expandStoreVec2()
1569     StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;  in expandStoreVec2()
1579     StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai  : Hexagon::V6_vS32b_ai_128B;  in expandStoreVec2()
1581     StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;  in expandStoreVec2()
1610   bool Is128B = HST.useHVXDblOps();  in expandLoadVec2()  local
1611   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandLoadVec2()
1620     LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai  : Hexagon::V6_vL32b_ai_128B;  in expandLoadVec2()
1622     LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;  in expandLoadVec2()
1631     LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai  : Hexagon::V6_vL32b_ai_128B;  in expandLoadVec2()
1633     LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;  in expandLoadVec2()
1659   bool Is128B = HST.useHVXDblOps();  in expandStoreVec()  local
1660   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandStoreVec()
1668     StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;  in expandStoreVec()
1670     StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;  in expandStoreVec()
1696   bool Is128B = HST.useHVXDblOps();  in expandLoadVec()  local
1697   auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass  in expandLoadVec()
1705     LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B;  in expandLoadVec()
1707     LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B;  in expandLoadVec()