Lines Matching refs:v64i32
209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
425 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
426 LocVT = MVT::v64i32; in RetCC_Hexagon()
427 ValVT = MVT::v64i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
497 } else if (LocVT == MVT::v64i32) { in RetCC_HexagonVector()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1140 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1771 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); in HexagonTargetLowering()
2554 MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32; in LowerCONCAT_VECTORS()
2898 case MVT::v64i32: in getRegForInlineAsmConstraint()
3036 case MVT::v64i32: in allowsMisalignedMemoryAccesses()
3073 case MVT::v64i32: in findRepresentativeClass()