Lines Matching refs:DoubleRegs
296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
432 def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
433 def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
437 def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
440 def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
443 def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
458 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
476 DoubleRegs, 0b0100>;
485 DoubleRegs, 0b0010>;
490 def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
491 def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
495 def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
629 defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
721 def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
794 def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
815 defm : T_StoreAbsReg_Pats <S4_storerd_ur, DoubleRegs, i64, store>;
1032 defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
1378 def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
1382 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
1383 (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
1870 def: Pat<(i64 (and (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1871 (A4_andnp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1872 def: Pat<(i64 (or (i64 DoubleRegs:$Rs), (i64 (not (i64 DoubleRegs:$Rt))))),
1873 (A4_ornp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
1966 def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
1995 : SInst <(outs DoubleRegs:$Rxx),
1996 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1998 [(set (i64 DoubleRegs:$Rxx),
1999 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2000 (i64 DoubleRegs:$Rtt))))],
2019 : SInst <(outs DoubleRegs:$Rdd),
2020 (ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2043 : SInst <(outs DoubleRegs:$Rxx),
2044 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
2065 : SInst <(outs DoubleRegs:$Rxx),
2066 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
2136 def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
2152 def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
2348 def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
2571 (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
2698 : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
2699 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
2722 : SInst <(outs DoubleRegs:$Rxx),
2723 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
3556 defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
3602 def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
3706 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
3759 defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3789 def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
3923 def Insert4 : PseudoM<(outs DoubleRegs:$dst), (ins IntRegs:$a, IntRegs:$b,
3926 [(set (i64 DoubleRegs:$dst),
3942 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3962 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
3980 (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
3986 (ins DoubleRegs:$Rs, IntRegs:$Rt),