Lines Matching refs:v2i16

18 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
40 defm : bitconvert_32<v2i16, i32>;
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
268 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
339 def: Pat<(v2i16 (trunc V2I32:$Rs)),
360 // Sign extends a v2i16 into a v2i32.
361 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
365 // Multiplies two v2i16 and returns a v2i32.  We are using here the
370 // Multiplies two v2i16 vectors: as Hexagon does not have a multiply
372 // multiply vmpyh that takes two v2i16 and returns a v2i32.  This is
373 // then truncated to fit this back into a v2i16 and to simulate the
378 def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
447 // Truncated store from v2i32 to v2i16.
450     [{ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2i16; }]>;
460 // Zero and sign extended load from v2i8 into v2i16.
467 def: Pat<(v2i16 (zextloadv2i8 I32:$Rs)),
470 def: Pat<(v2i16 (sextloadv2i8 I32:$Rs)),