Lines Matching refs:v32i32
65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
178 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
184 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
834 (v32i32 (HEXAGON_V6_hi_128B VecDblRegs128B:$Vdd)),
835 (v32i32 (HEXAGON_V6_lo_128B VecDblRegs128B:$Vdd))))>,