Lines Matching refs:SLOT0

17 //    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
27 def SLOT0       : FuncUnit;
100       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
137         InstrItinData<LD_tc_ld_SLOT01        , [InstrStage<1, [SLOT0, SLOT1]>]>,
138         InstrItinData<LD_tc_ld_SLOT0         , [InstrStage<1, [SLOT0]>]>,
139         InstrItinData<LD_tc_3or4stall_SLOT0  , [InstrStage<1, [SLOT0]>]>,
151         InstrItinData<ST_tc_st_SLOT01        , [InstrStage<1, [SLOT0, SLOT1]>]>,
153         InstrItinData<ST_tc_st_SLOT0         , [InstrStage<1, [SLOT0]>]>,
154         InstrItinData<ST_tc_ld_SLOT0         , [InstrStage<1, [SLOT0]>]>,
169         InstrItinData<ST_tc_3stall_SLOT0     , [InstrStage<1, [SLOT0]>]>,
172         InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
175         InstrItinData<V2LDST_tc_st_SLOT0     , [InstrStage<1, [SLOT0]>]>,
176         InstrItinData<V2LDST_tc_ld_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
177         InstrItinData<V2LDST_tc_st_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
178         InstrItinData<V4LDST_tc_st_SLOT0     , [InstrStage<1, [SLOT0]>]>,
179         InstrItinData<V4LDST_tc_ld_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
180         InstrItinData<V4LDST_tc_st_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
182         InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
189                      [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
192         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,