Lines Matching refs:SLOT0

17 //    | SLOT0     |  LD       ST    ALU32     MEMOP     NV    SYSTEM |
43       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
83                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
86         InstrItinData<LD_tc_ld_SLOT01      , [InstrStage<3, [SLOT0, SLOT1]>]>,
87         InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
88         InstrItinData<LD_tc_ld_SLOT0       , [InstrStage<3, [SLOT0]>]>,
99         InstrItinData<ST_tc_st_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>]>,
100         InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
101         InstrItinData<ST_tc_ld_SLOT0    , [InstrStage<3, [SLOT0]>]>,
102         InstrItinData<ST_tc_st_SLOT0    , [InstrStage<1, [SLOT0]>]>,
105         InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
106         InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
107         InstrItinData<SUBINSN_tc_ld_SLOT0    , [InstrStage<3, [SLOT0]>]>,
108         InstrItinData<SUBINSN_tc_1_SLOT01    , [InstrStage<1, [SLOT0, SLOT1]>]>,
110                               [InstrStage<2, [SLOT0, SLOT1]>]>,
111         InstrItinData<SUBINSN_tc_ld_SLOT01   , [InstrStage<3, [SLOT0, SLOT1]>]>,
112         InstrItinData<SUBINSN_tc_st_SLOT01   , [InstrStage<1, [SLOT0, SLOT1]>]>,
127         InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
130         InstrItinData<V2LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>]>,
131         InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
132         InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
133         InstrItinData<V4LDST_tc_st_SLOT0  , [InstrStage<1, [SLOT0]>]>,
134         InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
135         InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
142                       [InstrStage<3, [SLOT0, SLOT1]>]>,
148                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
153         InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
154         InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
155         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,