659   MachineOperand &Op1 = MI->getOperand(1);  in splitImmediate()  local
660   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
661   uint64_t V = Op1.getImm();  in splitImmediate()
687   MachineOperand &Op1 = MI->getOperand(1);  in splitCombine()  local
697   if (Op1.isImm()) {  in splitCombine()
699       .addImm(Op1.getImm());  in splitCombine()
700   } else if (Op1.isReg()) {  in splitCombine()
702       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
720   MachineOperand &Op1 = MI->getOperand(1);  in splitExt()  local
721   assert(Op0.isReg() && Op1.isReg());  in splitExt()
728   unsigned RS = getRegState(Op1);  in splitExt()
731     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
733     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
741   MachineOperand &Op1 = MI->getOperand(1);  in splitShift()  local
743   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
762   unsigned RS = getRegState(Op1);  in splitShift()
771       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
773       .addReg(Op1.getReg(), RS, HiSR);  in splitShift()
796         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
799         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
802         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
808         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
814         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
819         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
824         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
830       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
836         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
842         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
845         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
848         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
853         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
865   MachineOperand &Op1 = MI->getOperand(1);  in splitAslOr()  local
868   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
882   unsigned RS1 = getRegState(Op1);  in splitAslOr()
906       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
909       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
913       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
923       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
935       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
937       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
946       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
948       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()