Lines Matching refs:v4i8

1318 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1320 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1324 def : DSPPat<(v4i8 (load addr:$a)),
1325              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1328 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1342 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1343 def : DSPBinPat<ADDU_QB, v4i8, add>;
1344 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1345 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1362 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1363 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1364 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1365 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1366 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1367 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1400 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1401 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1402 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1403 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1404 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1405 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1413 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1414 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1415 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1416 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1417 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1418 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;