Lines Matching refs:addReg
171 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
175 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
326 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
335 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
358 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
376 .addReg(MFI->getGlobalBaseReg()) in materializeGV()
382 .addReg(DestReg) in materializeGV()
393 .addReg(MFI->getGlobalBaseReg()) in materializeExternalCallSym()
611 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
612 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
617 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
618 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
622 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
626 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
631 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
632 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
637 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
642 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
646 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
651 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
652 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
657 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
658 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
704 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
705 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
706 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( in emitCmp()
709 .addReg(RegWithOne) in emitCmp()
710 .addReg(Mips::FCC0) in emitCmp()
711 .addReg(RegWithZero); in emitCmp()
821 .addReg(SrcReg) in emitStore()
930 .addReg(CondReg) in selectBranch()
965 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1014 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
1016 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1040 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1079 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1175 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1243 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1320 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1323 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1327 MIB.addReg(Reg, RegState::Implicit); in fastLowerCall()
1361 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1371 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1372 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1373 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1374 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1381 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1382 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1393 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1394 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1395 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1396 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1398 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1399 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1401 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1402 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1403 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1514 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg); in selectRet()
1521 MIB.addReg(RetRegs[i], RegState::Implicit); in selectRet()
1589 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1590 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1600 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1603 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1636 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1689 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1690 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1752 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
1775 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
1860 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
1882 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1883 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rr()
1884 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
1885 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()