Lines Matching refs:getRegClassFor

1110   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));  in emitAtomicBinary()
1214   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitSignExtendToI32InReg()
1234   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicBinaryPartword()
1237     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicBinaryPartword()
1398   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));  in emitAtomicCmpSwap()
1488   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicCmpSwapPartword()
1491     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicCmpSwapPartword()
2131   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));  in lowerRETURNADDR()
3082       const TargetRegisterClass *RC = getRegClassFor(RegVT);  in LowerFormalArguments()
3150             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));  in LowerFormalArguments()
3483     RC = getRegClassFor(VT);  in parseRegForInlineAsmConstraint()
3492     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);  in parseRegForInlineAsmConstraint()
3495     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);  in parseRegForInlineAsmConstraint()
3753   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in copyByValRegs()
3875   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in writeVarArgRegs()