Lines Matching refs:ShiftReg

8543   unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8588   BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8597       .addReg(incr).addReg(ShiftReg);
8605       .addReg(Mask2Reg).addReg(ShiftReg);
8630     .addReg(ShiftReg);
9258     unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
9313     BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
9322         .addReg(newval).addReg(ShiftReg);
9324         .addReg(oldval).addReg(ShiftReg);
9333         .addReg(Mask2Reg).addReg(ShiftReg);
9373       .addReg(ShiftReg);