Lines Matching refs:hasVSX
532 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) { in PPCTargetLowering()
559 if (Subtarget.hasVSX()) { in PPCTargetLowering()
2957 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
3385 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
7464 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
7709 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
9460 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
9482 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
10312 if (N->getValueType(0) != MVT::v2f64 || !Subtarget.hasVSX()) in DAGCombineBuildVector()
10636 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10650 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10967 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) { in PerformDAGCombine()
10980 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) { in PerformDAGCombine()
11444 Constraint == "wf") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
11446 } else if (Constraint == "ws" && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
11908 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector()))) in getOptimalMemOpType()
11995 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
12059 if (Subtarget.hasVSX() || Subtarget.hasQPX()) in shouldExpandBuildVectorWithShuffles()