Lines Matching refs:isPPC64
78 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() local
79 setMinStackArgumentAlignment(isPPC64 ? 8:4); in PPCTargetLowering()
115 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
118 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
121 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
266 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
314 if (isPPC64) { in PPCTargetLowering()
333 if (Subtarget.isSVR4ABI() && !isPPC64) in PPCTargetLowering()
378 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) in PPCTargetLowering()
566 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
833 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
835 if (!isPPC64) { in PPCTargetLowering()
847 if (!isPPC64) { in PPCTargetLowering()
854 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
996 unsigned Align = Subtarget.isPPC64() ? 8 : 4; in getByValTypeAlignment()
1912 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
1964 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
2135 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerConstantPool()
2164 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerJumpTable()
2193 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerBlockAddress()
2221 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddress()
2306 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerGlobalAddress()
2411 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
2510 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
2534 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE() local
2544 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, in LowerINIT_TRAMPOLINE()
2545 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
2569 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { in LowerVASTART()
2865 if (Subtarget.isPPC64()) in LowerFormalArguments()
3555 bool isPPC64 = PtrVT == MVT::i64; in LowerFormalArguments_Darwin() local
3559 unsigned PtrByteSize = isPPC64 ? 8 : 4; in LowerFormalArguments_Darwin()
3584 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
3594 if (!isVarArg && !isPPC64) { in LowerFormalArguments_Darwin()
3660 if (isVarArg || isPPC64) { in LowerFormalArguments_Darwin()
3692 if (isPPC64) in LowerFormalArguments_Darwin()
3715 if (isPPC64) in LowerFormalArguments_Darwin()
3740 if (!isPPC64) { in LowerFormalArguments_Darwin()
3783 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) in LowerFormalArguments_Darwin()
3801 ArgOffset += isPPC64 ? 8 : ObjSize; in LowerFormalArguments_Darwin()
3823 if (!isVarArg && !isPPC64) { in LowerFormalArguments_Darwin()
3885 if (isPPC64) in LowerFormalArguments_Darwin()
3968 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64()); in needStackSlotPassParameters()
4188 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr() local
4189 int SlotSize = isPPC64 ? 8 : 4; in EmitTailCallStoreFPAndRetAddr()
4193 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
4218 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, in CalculateTailCallArgDest() argument
4224 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
4241 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
4278 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, in LowerMemOpCallTo() argument
4285 if (isPPC64) in LowerMemOpCallTo()
4295 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, in LowerMemOpCallTo()
4345 bool isPPC64 = Subtarget.isPPC64(); in PrepareCall() local
4356 if (!isSVR4ABI || !isPPC64) in PrepareCall()
4372 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64; in PrepareCall()
4416 if (isSVR4ABI && isPPC64 && !isELFv2ABI) { in PrepareCall()
4501 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest) in PrepareCall()
4505 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); in PrepareCall()
4525 if (isSVR4ABI && isPPC64 && !isPatchPoint) { in PrepareCall()
4600 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64()) in FinishCall()
4642 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() && in FinishCall()
4702 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
4733 if (Subtarget.isPPC64()) in LowerCall()
5632 bool isPPC64 = PtrVT == MVT::i64; in LowerCall_Darwin() local
5633 unsigned PtrByteSize = isPPC64 ? 8 : 4; in LowerCall_Darwin()
5666 if (!isVarArg && !isPPC64) { in LowerCall_Darwin()
5720 if (isPPC64) in LowerCall_Darwin()
5748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
5767 if (isPPC64 && Arg.getValueType() == MVT::i32) { in LowerCall_Darwin()
5841 isPPC64, isTailCall, false, MemOpChains, in LowerCall_Darwin()
5864 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ in LowerCall_Darwin()
5880 !isPPC64) // PPC64 has 64-bit GPR's obviously :) in LowerCall_Darwin()
5885 isPPC64, isTailCall, false, MemOpChains, in LowerCall_Darwin()
5887 if (isPPC64) in LowerCall_Darwin()
5943 isPPC64, isTailCall, true, MemOpChains, in LowerCall_Darwin()
5969 isPPC64, isTailCall, true, MemOpChains, in LowerCall_Darwin()
5987 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : in LowerCall_Darwin()
6114 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE() local
6115 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
6137 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex() local
6150 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false); in getReturnAddrFrameIndex()
6160 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex() local
6173 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); in getFramePointerFrameIndex()
6474 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
6647 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6830 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
7776 bool is64bit = Subtarget.isPPC64(); in LowerINTRINSIC_WO_CHAIN()
8342 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
8517 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
8709 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) { in emitEHSjLjSetJmp()
8722 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
8724 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
8727 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
8751 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
8754 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
8893 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() && in EmitInstrWithCustomInserter()
9231 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
10046 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
10615 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && in PerformDAGCombine()
10996 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && in PerformDAGCombine()
11207 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
11409 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
11413 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
11462 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
11608 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR() local
11615 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
11637 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR() local
11643 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
11645 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
11660 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName() local
11663 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || in getRegisterByName()
11664 (!isPPC64 && VT != MVT::i32)) in getRegisterByName()
11667 bool is64Bit = isPPC64 && VT == MVT::i64; in getRegisterByName()
11670 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2) in getRegisterByName()
11671 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 : in getRegisterByName()
11912 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
11951 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
12045 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
12050 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
12081 if (!Subtarget.isPPC64()) return; in initializeSplitCSR()