Lines Matching refs:def
25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
65 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
67 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
69 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
72 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
74 def ASR1 : SparcCtrlReg<1, "ASR1">;
75 def ASR2 : SparcCtrlReg<2, "ASR2">;
76 def ASR3 : SparcCtrlReg<3, "ASR3">;
77 def ASR4 : SparcCtrlReg<4, "ASR4">;
78 def ASR5 : SparcCtrlReg<5, "ASR5">;
79 def ASR6 : SparcCtrlReg<6, "ASR6">;
80 def ASR7 : SparcCtrlReg<7, "ASR7">;
81 def ASR8 : SparcCtrlReg<8, "ASR8">;
82 def ASR9 : SparcCtrlReg<9, "ASR9">;
83 def ASR10 : SparcCtrlReg<10, "ASR10">;
84 def ASR11 : SparcCtrlReg<11, "ASR11">;
85 def ASR12 : SparcCtrlReg<12, "ASR12">;
86 def ASR13 : SparcCtrlReg<13, "ASR13">;
87 def ASR14 : SparcCtrlReg<14, "ASR14">;
88 def ASR15 : SparcCtrlReg<15, "ASR15">;
89 def ASR16 : SparcCtrlReg<16, "ASR16">;
90 def ASR17 : SparcCtrlReg<17, "ASR17">;
91 def ASR18 : SparcCtrlReg<18, "ASR18">;
92 def ASR19 : SparcCtrlReg<19, "ASR19">;
93 def ASR20 : SparcCtrlReg<20, "ASR20">;
94 def ASR21 : SparcCtrlReg<21, "ASR21">;
95 def ASR22 : SparcCtrlReg<22, "ASR22">;
96 def ASR23 : SparcCtrlReg<23, "ASR23">;
97 def ASR24 : SparcCtrlReg<24, "ASR24">;
98 def ASR25 : SparcCtrlReg<25, "ASR25">;
99 def ASR26 : SparcCtrlReg<26, "ASR26">;
100 def ASR27 : SparcCtrlReg<27, "ASR27">;
101 def ASR28 : SparcCtrlReg<28, "ASR28">;
102 def ASR29 : SparcCtrlReg<29, "ASR29">;
103 def ASR30 : SparcCtrlReg<30, "ASR30">;
104 def ASR31 : SparcCtrlReg<31, "ASR31">;
107 def PSR : SparcCtrlReg<0, "PSR">;
108 def WIM : SparcCtrlReg<0, "WIM">;
109 def TBR : SparcCtrlReg<0, "TBR">;
111 def TPC : SparcCtrlReg<0, "TPC">;
112 def TNPC : SparcCtrlReg<1, "TNPC">;
113 def TSTATE : SparcCtrlReg<2, "TSTATE">;
114 def TT : SparcCtrlReg<3, "TT">;
115 def TICK : SparcCtrlReg<4, "TICK">;
116 def TBA : SparcCtrlReg<5, "TBA">;
117 def PSTATE : SparcCtrlReg<6, "PSTATE">;
118 def TL : SparcCtrlReg<7, "TL">;
119 def PIL : SparcCtrlReg<8, "PIL">;
120 def CWP : SparcCtrlReg<9, "CWP">;
121 def CANSAVE : SparcCtrlReg<10, "CANSAVE">;
122 def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">;
123 def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">;
124 def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
125 def WSTATE : SparcCtrlReg<14, "WSTATE">;
128 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
130 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
131 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
132 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
133 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
134 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
135 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
136 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
137 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
138 def O2 : Ri<10, "O2">, DwarfRegNum<[10]>;
139 def O3 : Ri<11, "O3">, DwarfRegNum<[11]>;
140 def O4 : Ri<12, "O4">, DwarfRegNum<[12]>;
141 def O5 : Ri<13, "O5">, DwarfRegNum<[13]>;
142 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>;
143 def O7 : Ri<15, "O7">, DwarfRegNum<[15]>;
144 def L0 : Ri<16, "L0">, DwarfRegNum<[16]>;
145 def L1 : Ri<17, "L1">, DwarfRegNum<[17]>;
146 def L2 : Ri<18, "L2">, DwarfRegNum<[18]>;
147 def L3 : Ri<19, "L3">, DwarfRegNum<[19]>;
148 def L4 : Ri<20, "L4">, DwarfRegNum<[20]>;
149 def L5 : Ri<21, "L5">, DwarfRegNum<[21]>;
150 def L6 : Ri<22, "L6">, DwarfRegNum<[22]>;
151 def L7 : Ri<23, "L7">, DwarfRegNum<[23]>;
152 def I0 : Ri<24, "I0">, DwarfRegNum<[24]>;
153 def I1 : Ri<25, "I1">, DwarfRegNum<[25]>;
154 def I2 : Ri<26, "I2">, DwarfRegNum<[26]>;
155 def I3 : Ri<27, "I3">, DwarfRegNum<[27]>;
156 def I4 : Ri<28, "I4">, DwarfRegNum<[28]>;
157 def I5 : Ri<29, "I5">, DwarfRegNum<[29]>;
158 def I6 : Ri<30, "FP">, DwarfRegNum<[30]>;
159 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
162 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
163 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
164 def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>;
165 def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>;
166 def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>;
167 def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>;
168 def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>;
169 def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>;
170 def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>;
171 def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>;
172 def F10 : Rf<10, "F10">, DwarfRegNum<[42]>;
173 def F11 : Rf<11, "F11">, DwarfRegNum<[43]>;
174 def F12 : Rf<12, "F12">, DwarfRegNum<[44]>;
175 def F13 : Rf<13, "F13">, DwarfRegNum<[45]>;
176 def F14 : Rf<14, "F14">, DwarfRegNum<[46]>;
177 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>;
178 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>;
179 def F17 : Rf<17, "F17">, DwarfRegNum<[49]>;
180 def F18 : Rf<18, "F18">, DwarfRegNum<[50]>;
181 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>;
182 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
183 def F21 : Rf<21, "F21">, DwarfRegNum<[53]>;
184 def F22 : Rf<22, "F22">, DwarfRegNum<[54]>;
185 def F23 : Rf<23, "F23">, DwarfRegNum<[55]>;
186 def F24 : Rf<24, "F24">, DwarfRegNum<[56]>;
187 def F25 : Rf<25, "F25">, DwarfRegNum<[57]>;
188 def F26 : Rf<26, "F26">, DwarfRegNum<[58]>;
189 def F27 : Rf<27, "F27">, DwarfRegNum<[59]>;
190 def F28 : Rf<28, "F28">, DwarfRegNum<[60]>;
191 def F29 : Rf<29, "F29">, DwarfRegNum<[61]>;
192 def F30 : Rf<30, "F30">, DwarfRegNum<[62]>;
193 def F31 : Rf<31, "F31">, DwarfRegNum<[63]>;
196 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
197 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
198 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
199 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
200 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
201 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
202 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
203 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
204 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
205 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
206 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
207 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>;
208 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>;
209 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>;
210 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>;
211 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
214 def C0 : Ri< 0, "C0">;
215 def C1 : Ri< 1, "C1">;
216 def C2 : Ri< 2, "C2">;
217 def C3 : Ri< 3, "C3">;
218 def C4 : Ri< 4, "C4">;
219 def C5 : Ri< 5, "C5">;
220 def C6 : Ri< 6, "C6">;
221 def C7 : Ri< 7, "C7">;
222 def C8 : Ri< 8, "C8">;
223 def C9 : Ri< 9, "C9">;
224 def C10 : Ri< 10, "C10">;
225 def C11 : Ri< 11, "C11">;
226 def C12 : Ri< 12, "C12">;
227 def C13 : Ri< 13, "C13">;
228 def C14 : Ri< 14, "C14">;
229 def C15 : Ri< 15, "C15">;
230 def C16 : Ri< 16, "C16">;
231 def C17 : Ri< 17, "C17">;
232 def C18 : Ri< 18, "C18">;
233 def C19 : Ri< 19, "C19">;
234 def C20 : Ri< 20, "C20">;
235 def C21 : Ri< 21, "C21">;
236 def C22 : Ri< 22, "C22">;
237 def C23 : Ri< 23, "C23">;
238 def C24 : Ri< 24, "C24">;
239 def C25 : Ri< 25, "C25">;
240 def C26 : Ri< 26, "C26">;
241 def C27 : Ri< 27, "C27">;
242 def C28 : Ri< 28, "C28">;
243 def C29 : Ri< 29, "C29">;
244 def C30 : Ri< 30, "C30">;
245 def C31 : Ri< 31, "C31">;
249 def D16 : SparcReg< 1, "F32">;
250 def D17 : SparcReg< 3, "F34">;
251 def D18 : SparcReg< 5, "F36">;
252 def D19 : SparcReg< 7, "F38">;
253 def D20 : SparcReg< 9, "F40">;
254 def D21 : SparcReg<11, "F42">;
255 def D22 : SparcReg<13, "F44">;
256 def D23 : SparcReg<15, "F46">;
257 def D24 : SparcReg<17, "F48">;
258 def D25 : SparcReg<19, "F50">;
259 def D26 : SparcReg<21, "F52">;
260 def D27 : SparcReg<23, "F54">;
261 def D28 : SparcReg<25, "F56">;
262 def D29 : SparcReg<27, "F58">;
263 def D30 : SparcReg<29, "F60">;
264 def D31 : SparcReg<31, "F62">;
267 def Q0 : Rq< 0, "F0", [D0, D1]>;
268 def Q1 : Rq< 4, "F4", [D2, D3]>;
269 def Q2 : Rq< 8, "F8", [D4, D5]>;
270 def Q3 : Rq<12, "F12", [D6, D7]>;
271 def Q4 : Rq<16, "F16", [D8, D9]>;
272 def Q5 : Rq<20, "F20", [D10, D11]>;
273 def Q6 : Rq<24, "F24", [D12, D13]>;
274 def Q7 : Rq<28, "F28", [D14, D15]>;
275 def Q8 : Rq< 1, "F32", [D16, D17]>;
276 def Q9 : Rq< 5, "F36", [D18, D19]>;
277 def Q10 : Rq< 9, "F40", [D20, D21]>;
278 def Q11 : Rq<13, "F44", [D22, D23]>;
279 def Q12 : Rq<17, "F48", [D24, D25]>;
280 def Q13 : Rq<21, "F52", [D26, D27]>;
281 def Q14 : Rq<25, "F56", [D28, D29]>;
282 def Q15 : Rq<29, "F60", [D30, D31]>;
285 def G0_G1 : Rdi<0, "G0", [G0, G1]>;
286 def G2_G3 : Rdi<2, "G2", [G2, G3]>;
287 def G4_G5 : Rdi<4, "G4", [G4, G5]>;
288 def G6_G7 : Rdi<6, "G6", [G6, G7]>;
289 def O0_O1 : Rdi<8, "O0", [O0, O1]>;
290 def O2_O3 : Rdi<10, "O2", [O2, O3]>;
291 def O4_O5 : Rdi<12, "O4", [O4, O5]>;
292 def O6_O7 : Rdi<14, "O6", [O6, O7]>;
293 def L0_L1 : Rdi<16, "L0", [L0, L1]>;
294 def L2_L3 : Rdi<18, "L2", [L2, L3]>;
295 def L4_L5 : Rdi<20, "L4", [L4, L5]>;
296 def L6_L7 : Rdi<22, "L6", [L6, L7]>;
297 def I0_I1 : Rdi<24, "I0", [I0, I1]>;
298 def I2_I3 : Rdi<26, "I2", [I2, I3]>;
299 def I4_I5 : Rdi<28, "I4", [I4, I5]>;
300 def I6_I7 : Rdi<30, "I6", [I6, I7]>;
303 def C0_C1 : Rdi<0, "C0", [C0, C1]>;
304 def C2_C3 : Rdi<2, "C2", [C2, C3]>;
305 def C4_C5 : Rdi<4, "C4", [C4, C5]>;
306 def C6_C7 : Rdi<6, "C6", [C6, C7]>;
307 def C8_C9 : Rdi<8, "C8", [C8, C9]>;
308 def C10_C11 : Rdi<10, "C10", [C10, C11]>;
309 def C12_C13 : Rdi<12, "C12", [C12, C13]>;
310 def C14_C15 : Rdi<14, "C14", [C14, C15]>;
311 def C16_C17 : Rdi<16, "C16", [C16, C17]>;
312 def C18_C19 : Rdi<18, "C18", [C18, C19]>;
313 def C20_C21 : Rdi<20, "C20", [C20, C21]>;
314 def C22_C23 : Rdi<22, "C22", [C22, C23]>;
315 def C24_C25 : Rdi<24, "C24", [C24, C25]>;
316 def C26_C27 : Rdi<26, "C26", [C26, C27]>;
317 def C28_C29 : Rdi<28, "C28", [C28, C29]>;
318 def C30_C31 : Rdi<30, "C30", [C30, C31]>;
328 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
336 def IntPair : RegisterClass<"SP", [v2i32], 64,
346 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
349 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
351 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
353 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
356 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
360 def ASRRegs : RegisterClass<"SP", [i32], 32,
364 def CoprocRegs : RegisterClass<"SP", [i32], 32,
368 def CoprocPair : RegisterClass<"SP", [v2i32], 64,
376 def PRRegs : RegisterClass<"SP", [i64], 64,