248 static void translateRegister(MCInst &mcInst, Reg reg) {  in translateRegister()  argument
257   mcInst.addOperand(MCOperand::createReg(llvmRegnum));  in translateRegister()
314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateSrcIndex()  argument
326   mcInst.addOperand(baseReg);  in translateSrcIndex()
330   mcInst.addOperand(segmentReg);  in translateSrcIndex()
339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {  in translateDstIndex()  argument
351   mcInst.addOperand(baseReg);  in translateDstIndex()
361 static void translateImmediate(MCInst &mcInst, uint64_t immediate,  in translateImmediate()  argument
419       switch (mcInst.getOpcode()) {  in translateImmediate()
447       mcInst.setOpcode(NewOpc);  in translateImmediate()
453       switch (mcInst.getOpcode()) {  in translateImmediate()
479       mcInst.setOpcode(NewOpc);  in translateImmediate()
484       switch (mcInst.getOpcode()) {  in translateImmediate()
608       mcInst.setOpcode(NewOpc);  in translateImmediate()
616     mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));  in translateImmediate()
619     mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));  in translateImmediate()
622     mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));  in translateImmediate()
625     mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));  in translateImmediate()
652                                mcInst, Dis))  in translateImmediate()
653     mcInst.addOperand(MCOperand::createImm(immediate));  in translateImmediate()
659     mcInst.addOperand(segmentReg);  in translateImmediate()
669 static bool translateRMRegister(MCInst &mcInst,  in translateRMRegister()  argument
691     mcInst.addOperand(MCOperand::createReg(X86::x)); break;  in translateRMRegister()
707 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,  in translateRMMemory()  argument
750     uint32_t Opcode = mcInst.getOpcode();  in translateRMMemory()
871   mcInst.addOperand(baseReg);  in translateRMMemory()
872   mcInst.addOperand(scaleAmount);  in translateRMMemory()
873   mcInst.addOperand(indexReg);  in translateRMMemory()
876                                insn.displacementSize, mcInst, Dis))  in translateRMMemory()
877     mcInst.addOperand(displacement);  in translateRMMemory()
878   mcInst.addOperand(segmentReg);  in translateRMMemory()
890 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,  in translateRM()  argument
917     return translateRMRegister(mcInst, insn);  in translateRM()
934     return translateRMMemory(mcInst, insn, Dis);  in translateRM()
943 static void translateFPRegister(MCInst &mcInst,  in translateFPRegister()  argument
945   mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));  in translateFPRegister()
954 static bool translateMaskRegister(MCInst &mcInst,  in translateMaskRegister()  argument
961   mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));  in translateMaskRegister()
972 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,  in translateOperand()  argument
980     translateRegister(mcInst, insn.reg);  in translateOperand()
983     return translateMaskRegister(mcInst, insn.writemask);  in translateOperand()
985     return translateRM(mcInst, operand, insn, Dis);  in translateOperand()
992     translateImmediate(mcInst,  in translateOperand()
999     return translateSrcIndex(mcInst, insn);  in translateOperand()
1001     return translateDstIndex(mcInst, insn);  in translateOperand()
1007     translateRegister(mcInst, insn.opcodeRegister);  in translateOperand()
1010     translateFPRegister(mcInst, insn.modRM & 7);  in translateOperand()
1013     translateRegister(mcInst, insn.vvvv);  in translateOperand()
1016     return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],  in translateOperand()
1027 static bool translateInstruction(MCInst &mcInst,  in translateInstruction()  argument
1035   mcInst.clear();  in translateInstruction()
1036   mcInst.setOpcode(insn.instructionID);  in translateInstruction()
1041     if(mcInst.getOpcode() == X86::REP_PREFIX)  in translateInstruction()
1042       mcInst.setOpcode(X86::XRELEASE_PREFIX);  in translateInstruction()
1043     else if(mcInst.getOpcode() == X86::REPNE_PREFIX)  in translateInstruction()
1044       mcInst.setOpcode(X86::XACQUIRE_PREFIX);  in translateInstruction()
1051       if (translateOperand(mcInst, Op, insn, Dis)) {  in translateInstruction()