Lines Matching refs:SrcInfo
799 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
803 (ins SrcInfo.FRC:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}",
804 [(set DestInfo.RC:$dst, (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)))]>,
809 (ins DestInfo.RC:$src0, DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
813 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
818 (ins DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
822 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
829 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
832 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
833 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
843 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
846 (SrcInfo.VT (scalar_to_vector
847 (SrcInfo.ScalarLdFrag addr:$src)))))>,
848 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
928 X86VectorVTInfo SrcInfo> {
929 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
931 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
6257 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6261 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6262 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6267 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6269 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6270 SrcInfo.RC:$src1)>;
6273 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6275 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6276 SrcInfo.RC:$src1)>;
6279 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6281 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6283 SrcInfo.RC:$src1)>;
6287 (ins x86memop:$dst, SrcInfo.RC:$src),
6292 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6298 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6302 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6303 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6304 addr:$dst, SrcInfo.RC:$src)>;
6306 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6307 (SrcInfo.VT SrcInfo.RC:$src)),
6308 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6309 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6312 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6315 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6316 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6317 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6318 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6319 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6320 (SrcInfo.VT SrcInfo.RC:$src))>;
6322 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6323 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6324 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6325 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6326 (SrcInfo.VT SrcInfo.RC:$src))>;
6486 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6489 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6490 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
7085 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
7088 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
7090 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
7091 (SrcInfo.VT SrcInfo.RC:$src2),
7094 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
7096 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
7097 (SrcInfo.VT (bitconvert
7098 (SrcInfo.LdFrag addr:$src2))),
7190 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
7193 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
7197 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
7199 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;