Lines Matching refs:src2
44 (ins VR128:$src1, VR128:$src2, VR128:$src3),
46 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
52 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
54 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
55 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
60 (ins VR256:$src1, VR256:$src2, VR256:$src3),
62 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
68 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
72 (OpVT256 (Op VR256:$src2, VR256:$src1,
148 (ins RC:$src1, RC:$src2, RC:$src3),
150 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
155 (ins RC:$src1, RC:$src2, x86memop:$src3),
157 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
180 (ins RC:$src1, RC:$src2, RC:$src3),
182 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
187 (ins RC:$src1, RC:$src2, memopr:$src3),
189 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
242 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
244 $src1, $src2, $src3), VR128)>;
246 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
248 $src1, $src2, $src3), VR128)>;
272 (ins RC:$src1, RC:$src2, RC:$src3),
274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
278 (ins RC:$src1, RC:$src2, x86memop:$src3),
280 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
281 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
284 (ins RC:$src1, x86memop:$src2, RC:$src3),
286 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
288 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
292 (ins RC:$src1, RC:$src2, RC:$src3),
294 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
303 (ins VR128:$src1, VR128:$src2, VR128:$src3),
305 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
307 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
309 (ins VR128:$src1, VR128:$src2, memop:$src3),
311 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
312 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
315 (ins VR128:$src1, memop:$src2, VR128:$src3),
317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
319 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
328 (ins VR128:$src1, VR128:$src2, VR128:$src3),
330 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
332 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
335 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
337 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
338 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
341 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
345 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
348 (ins VR256:$src1, VR256:$src2, VR256:$src3),
350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
352 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
355 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
358 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
361 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
363 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
365 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
369 (ins VR128:$src1, VR128:$src2, VR128:$src3),
371 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
373 (ins VR256:$src1, VR256:$src2, VR256:$src3),
375 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,